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clk: mediatek: add 13mhz clock for MT8173 

Add 13mhz clock used by GPT timer in infracfg.

Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
This commit is contained in:
Joe.C 2015-07-13 17:32:48 +08:00 committed by James Liao
parent 9ffecb1028
commit 2d61fe0fc7
2 changed files with 7 additions and 1 deletions
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5
drivers/clk/mediatek/clk-mt8173.c
View File

@ -619,6 +619,10 @@ static const struct mtk_gate infra_clks[] __initconst = {
GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
};
static const struct mtk_fixed_factor infra_divs[] __initconst = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static const struct mtk_gate_regs peri0_cg_regs = {
.set_ofs = 0x0008,
.clr_ofs = 0x0010,
@ -754,6 +758,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)

3
include/dt-bindings/clock/mt8173-clk.h
View File

@ -187,7 +187,8 @@
#define CLK_INFRA_CEC 9
#define CLK_INFRA_PMICSPI 10
#define CLK_INFRA_PMICWRAP 11
#define CLK_INFRA_NR_CLK 12
#define CLK_INFRA_CLK_13M 12
#define CLK_INFRA_NR_CLK 13
/* PERI_SYS */