mirror of https://gitee.com/openkylin/linux.git
staging: rtl8192u: fix braces in r8192U.h
This patch fixes the whitespace around braces and brace position, and corrects the following checkpatch errors: ERROR: space required after that close brace '}' ERROR: space required before the open brace '{' ERROR: that open brace { should be on the previous line ERROR: open brace '{' following enum go on the same line Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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4e0be66853
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2da4fc24f5
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@ -88,7 +88,7 @@ extern u32 rt_global_debug_component;
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do { if (rt_global_debug_component & component) \
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printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
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##args);\
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}while(0);
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} while(0);
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#define COMP_TRACE BIT0 /* Function call tracing. */
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#define COMP_DBG BIT1
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@ -142,13 +142,11 @@ do { if (rt_global_debug_component & component) \
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* please set ieee80211_debug_level to DATA|BA
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*/
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#define RT_DEBUG_DATA(level, data, datalen) \
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do{ if ((rt_global_debug_component & (level)) == (level)) \
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{ \
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do { if ((rt_global_debug_component & (level)) == (level)) { \
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int i; \
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u8 *pdata = (u8 *) data; \
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printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__); \
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for(i=0; i<(int)(datalen); i++) \
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{ \
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for(i=0; i<(int)(datalen); i++) { \
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printk("%2x ", pdata[i]); \
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if ((i+1)%16 == 0) printk("\n"); \
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} \
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@ -246,7 +244,7 @@ typedef struct _tx_desc_819x_usb {
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u32 Reserved5;
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u32 Reserved6;
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u32 Reserved7;
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}tx_desc_819x_usb, *ptx_desc_819x_usb;
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} tx_desc_819x_usb, *ptx_desc_819x_usb;
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#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
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typedef struct _tx_desc_819x_usb_aggr_subframe {
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@ -270,7 +268,7 @@ typedef struct _tx_desc_819x_usb_aggr_subframe {
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u8 SecType:2;
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u8 PacketID:7;
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u8 OWN:1;
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}tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
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} tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
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#endif
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@ -300,7 +298,7 @@ typedef struct _tx_desc_cmd_819x_usb {
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u32 Reserved6;
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u32 Reserved7;
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u32 Reserved8;
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}tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
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} tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
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typedef struct _tx_fwinfo_819x_usb {
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@ -334,15 +332,15 @@ typedef struct _tx_fwinfo_819x_usb {
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u32 TxAGCSign:1;
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u32 Tx_INFO_RSVD:6;
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u32 PacketID:13;
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}tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
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} tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
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typedef struct rtl8192_rx_info {
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struct urb *urb;
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struct net_device *dev;
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u8 out_pipe;
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}rtl8192_rx_info ;
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} rtl8192_rx_info ;
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typedef struct rx_desc_819x_usb{
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typedef struct rx_desc_819x_usb {
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/* DOWRD 0 */
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u16 Length:14;
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u16 CRC32:1;
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@ -355,10 +353,10 @@ typedef struct rx_desc_819x_usb{
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/* DWORD 1 */
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u32 Reserved2;
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}rx_desc_819x_usb, *prx_desc_819x_usb;
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} rx_desc_819x_usb, *prx_desc_819x_usb;
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#ifdef USB_RX_AGGREGATION_SUPPORT
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typedef struct _rx_desc_819x_usb_aggr_subframe{
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typedef struct _rx_desc_819x_usb_aggr_subframe {
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/* DOWRD 0 */
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u16 Length:14;
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u16 CRC32:1;
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@ -372,10 +370,10 @@ typedef struct _rx_desc_819x_usb_aggr_subframe{
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u8 Reserved1:4;
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u8 Reserved2;
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u16 Reserved3;
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}rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
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} rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
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#endif
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typedef struct rx_drvinfo_819x_usb{
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typedef struct rx_drvinfo_819x_usb {
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/* DWORD 0 */
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u16 Reserved1:12;
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u16 PartAggr:1;
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@ -396,7 +394,7 @@ typedef struct rx_drvinfo_819x_usb{
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/* DWORD 1 */
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u32 TSFL;
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}rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
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} rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
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/* Support till 64 bit bus width OS */
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#define MAX_DEV_ADDR_SIZE 8
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@ -422,53 +420,52 @@ typedef struct rx_drvinfo_819x_usb{
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/* Octets for crc32 (FCS, ICV) */
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#define scrclng 4
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typedef enum rf_optype
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{
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typedef enum rf_optype {
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RF_OP_By_SW_3wire = 0,
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RF_OP_By_FW,
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RF_OP_MAX
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}rf_op_type;
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} rf_op_type;
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/* 8190 Loopback Mode definition */
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typedef enum _rtl819xUsb_loopback{
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typedef enum _rtl819xUsb_loopback {
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RTL819xU_NO_LOOPBACK = 0,
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RTL819xU_MAC_LOOPBACK = 1,
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RTL819xU_DMA_LOOPBACK = 2,
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RTL819xU_CCK_LOOPBACK = 3,
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}rtl819xUsb_loopback_e;
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} rtl819xUsb_loopback_e;
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/* due to rtl8192 firmware */
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typedef enum _desc_packet_type_e{
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typedef enum _desc_packet_type_e {
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DESC_PACKET_TYPE_INIT = 0,
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DESC_PACKET_TYPE_NORMAL = 1,
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}desc_packet_type_e;
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} desc_packet_type_e;
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typedef enum _firmware_status{
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typedef enum _firmware_status {
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FW_STATUS_0_INIT = 0,
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FW_STATUS_1_MOVE_BOOT_CODE = 1,
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FW_STATUS_2_MOVE_MAIN_CODE = 2,
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FW_STATUS_3_TURNON_CPU = 3,
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FW_STATUS_4_MOVE_DATA_CODE = 4,
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FW_STATUS_5_READY = 5,
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}firmware_status_e;
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} firmware_status_e;
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typedef struct _rt_firmare_seg_container {
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u16 seg_size;
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u8 *seg_ptr;
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}fw_seg_container, *pfw_seg_container;
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typedef struct _rt_firmware{
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} fw_seg_container, *pfw_seg_container;
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typedef struct _rt_firmware {
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firmware_status_e firmware_status;
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u16 cmdpacket_frag_thresold;
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#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
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u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u16 firmware_buf_size;
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}rt_firmware, *prt_firmware;
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} rt_firmware, *prt_firmware;
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/* Add this to 9100 bytes to receive A-MSDU from RT-AP */
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#define MAX_RECEIVE_BUFFER_SIZE 9100
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typedef struct _rt_firmware_info_819xUsb{
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typedef struct _rt_firmware_info_819xUsb {
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u8 sz_info[16];
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}rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
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} rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
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/* Firmware Queue Layout */
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#define NUM_OF_FIRMWARE_QUEUE 10
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@ -550,7 +547,7 @@ typedef struct buffer {
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} buffer;
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typedef struct rtl_reg_debug{
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typedef struct rtl_reg_debug {
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unsigned int cmd;
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struct {
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unsigned char type;
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@ -559,7 +556,7 @@ typedef struct rtl_reg_debug{
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unsigned char length;
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} head;
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unsigned char buf[0xff];
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}rtl_reg_debug;
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} rtl_reg_debug;
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@ -570,13 +567,13 @@ typedef struct _rt_9x_tx_rate_history {
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u32 cck[4];
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u32 ofdm[8];
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u32 ht_mcs[4][16];
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}rt_tx_rahis_t, *prt_tx_rahis_t;
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} rt_tx_rahis_t, *prt_tx_rahis_t;
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typedef struct _RT_SMOOTH_DATA_4RF {
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char elements[4][100]; /* array to store values */
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u32 index; /* index to current array to store */
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u32 TotalNum; /* num of valid elements */
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u32 TotalVal[4]; /* sum of valid elements */
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}RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
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} RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
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/* This maybe changed for D-cut larger aggregation size */
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#define MAX_8192U_RX_SIZE 8192
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@ -693,9 +690,9 @@ typedef struct ChnlAccessSetting {
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u16 EIFS_Timer;
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u16 CWminIndex;
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u16 CWmaxIndex;
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}*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
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} *PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
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typedef struct _BB_REGISTER_DEFINITION{
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typedef struct _BB_REGISTER_DEFINITION {
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/* set software control: 0x870~0x877 [8 bytes] */
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u32 rfintfs;
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/* readback data: 0x8e0~0x8e7 [8 bytes] */
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@ -740,15 +737,15 @@ typedef struct _BB_REGISTER_DEFINITION{
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u32 rfTxAFE;
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/* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */
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u32 rfLSSIReadBack;
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}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
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} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
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typedef enum _RT_RF_TYPE_819xU{
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typedef enum _RT_RF_TYPE_819xU {
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RF_TYPE_MIN = 0,
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RF_8225,
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RF_8256,
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RF_8258,
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RF_PSEUDO_11N = 4,
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}RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
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} RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
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typedef struct _rate_adaptive {
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u8 rate_adaptive_disabled;
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@ -810,7 +807,7 @@ typedef struct _phy_ofdm_rx_status_report_819xusb {
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u8 max_ex_pwr;
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u8 sgi_en;
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u8 rxsc_sgien_exflg;
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}phy_sts_ofdm_819xusb_t;
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} phy_sts_ofdm_819xusb_t;
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typedef struct _phy_cck_rx_status_report_819xusb {
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/* For CCK rate descriptor. This is an unsigned 8:1 variable.
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@ -819,18 +816,17 @@ typedef struct _phy_cck_rx_status_report_819xusb {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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}phy_sts_cck_819xusb_t;
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} phy_sts_cck_819xusb_t;
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typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
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typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag {
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u8 reserved:4;
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u8 rxsc:2;
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u8 sgi_en:1;
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u8 ex_intf_flag:1;
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}phy_ofdm_rx_status_rxsc_sgien_exintfflag;
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} phy_ofdm_rx_status_rxsc_sgien_exintfflag;
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typedef enum _RT_CUSTOMER_ID
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{
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typedef enum _RT_CUSTOMER_ID {
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RT_CID_DEFAULT = 0,
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RT_CID_8187_ALPHA0 = 1,
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RT_CID_8187_SERCOMM_PS = 2,
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RT_CID_Nettronix = 11,
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RT_CID_DLINK = 12,
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RT_CID_PRONET = 13,
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}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
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} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
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/*
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* ==========================================================================
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@ -853,7 +849,7 @@ typedef enum _RT_CUSTOMER_ID
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* ==========================================================================
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*/
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typedef enum _LED_STRATEGY_8190{
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typedef enum _LED_STRATEGY_8190 {
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SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
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SW_LED_MODE1, /* SW control for PCI Express */
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SW_LED_MODE2, /* SW control for Cameo. */
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SW_LED_MODE4, /* SW control for Netcore. */
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/* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
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HW_LED,
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}LED_STRATEGY_8190, *PLED_STRATEGY_8190;
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} LED_STRATEGY_8190, *PLED_STRATEGY_8190;
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typedef enum _RESET_TYPE {
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RESET_TYPE_NORESET = 0x00,
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} RESET_TYPE;
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/* The simple tx command OP code. */
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typedef enum _tag_TxCmd_Config_Index{
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typedef enum _tag_TxCmd_Config_Index {
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TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
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TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
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TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
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TXCMD_SET_RX_RSSI = 0xFF900004,
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TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
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TXCMD_XXXX_CTRL,
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}DCMD_TXCMD_OP;
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} DCMD_TXCMD_OP;
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typedef struct r8192_priv {
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struct usb_device *udev;
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/* If TCR reports card V B/C, this discriminates */
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u8 card_8192_version;
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short enable_gpio0;
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enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
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enum card_type {
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PCI, MINIPCI, CARDBUS, USB
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} card_type;
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short hw_plcp_len;
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short plcp_preamble_mode;
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struct delayed_work gpio_change_rf_wq;
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struct delayed_work initialgain_operate_wq;
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struct workqueue_struct *priv_wq;
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}r8192_priv;
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} r8192_priv;
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/* For rtl8187B */
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typedef enum{
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UART_PRIORITY
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} priority_t;
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typedef enum{
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typedef enum {
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NIC_8192U = 1,
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NIC_8190P = 2,
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NIC_8192E = 3,
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} nic_t;
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} nic_t;
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#ifdef JOHN_HWSEC
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