mirror of https://gitee.com/openkylin/linux.git
drm/tegra: Changes for v4.20-rc1
This contains initial Tegra194 support as well as a couple of fixes for DMA/IOMMU integration. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlutQZcTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoS1QD/48ft2dEY9xa7fB2z/jXQ3krtGX0OMv aWaR4Wb30FJxwT5B8u6hIrzxXZFIk5kU9IANErdYwFe95mjQNIpxNgUdfvK5xA7b hG4MQkUsYm/xNitnbAfNDEaZ3GK4Z3OTMC0k6Hk9EIY3gMfwirmG51ge7fMF1+l2 0ZHmWP5E6ONiRJB5HByT635un71icvLQfpfl5FhCNva0LjXZvIrxB68F+X8O8PMR ZrQ/7bcfYMsgZA9B1TI3NjfKeb3IZbbTVFgrmvww/ZtOJnZR4wbMdr6TavQlJ2Yc Sbg3/q/jSMH8TzBcdMd6lLfi2xkOHig/pL8het+JpzzvZJb/fW6536o4mQYSfqlq B8Hep8vhHIP+/oOcH5V35184xCKDeZrk67yj4GMak27vSJXEREZMidVwyK6G4zbx v0Sx8MV7YQbdYLOS9plSRnqha62isFUfN3dEg4+k0SwFFuedkX2RFQNgpja2ZsLo OKQeUFDa1dEs/hePR6RcmWVIPxl+dhmEyU4plFmGzY/MjyrndqBhew1DrUa1GaLJ 9QOmOXhoQSZLB0DIim/CkcuuSMpqv4TmP4mHJrRVgu+mBkyhvBtdW9ANhsRaM7LF O7MPs+vypCyxrNukKNoWdG2VZBtXJ8Uuk4jVtSu1ttY/cSD92Ygd/0B38jmqHQxW 22bIZJv9YcR3mg== =1zNu -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-4.20-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.20-rc1 This contains initial Tegra194 support as well as a couple of fixes for DMA/IOMMU integration. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180927205051.30017-1-thierry.reding@gmail.com
This commit is contained in:
Dave Airlie
commit
2de0b0a158
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@ -1988,6 +1988,28 @@ static int tegra_dc_init(struct host1x_client *client)
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struct drm_plane *cursor = NULL;
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int err;
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/*
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* XXX do not register DCs with no window groups because we cannot
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* assign a primary plane to them, which in turn will cause KMS to
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* crash.
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*/
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if (dc->soc->wgrps) {
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bool has_wgrps = false;
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unsigned int i;
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for (i = 0; i < dc->soc->num_wgrps; i++) {
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const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
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if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) {
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has_wgrps = true;
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break;
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}
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}
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if (!has_wgrps)
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return 0;
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}
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dc->syncpt = host1x_syncpt_request(client, flags);
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if (!dc->syncpt)
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dev_warn(dc->dev, "failed to allocate syncpoint\n");
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@ -2234,8 +2256,59 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
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.num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
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};
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static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
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{
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.index = 0,
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.dc = 0,
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.windows = (const unsigned int[]) { 0 },
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.num_windows = 1,
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}, {
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.index = 1,
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.dc = 1,
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.windows = (const unsigned int[]) { 1 },
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.num_windows = 1,
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}, {
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.index = 2,
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.dc = 1,
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.windows = (const unsigned int[]) { 2 },
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.num_windows = 1,
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}, {
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.index = 3,
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.dc = 2,
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.windows = (const unsigned int[]) { 3 },
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.num_windows = 1,
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}, {
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.index = 4,
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.dc = 2,
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.windows = (const unsigned int[]) { 4 },
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.num_windows = 1,
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}, {
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.index = 5,
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.dc = 2,
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.windows = (const unsigned int[]) { 5 },
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.num_windows = 1,
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},
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};
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static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
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.supports_background_color = true,
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.supports_interlacing = true,
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.supports_cursor = true,
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.supports_block_linear = true,
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.has_legacy_blending = false,
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.pitch_align = 64,
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.has_powergate = false,
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.coupled_pm = false,
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.has_nvdisplay = true,
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.wgrps = tegra194_dc_wgrps,
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.num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
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};
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static const struct of_device_id tegra_dc_of_match[] = {
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{
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.compatible = "nvidia,tegra194-dc",
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.data = &tegra194_dc_soc_info,
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}, {
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.compatible = "nvidia,tegra186-dc",
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.data = &tegra186_dc_soc_info,
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}, {
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@ -300,7 +300,7 @@ int tegra_dc_rgb_exit(struct tegra_dc *dc);
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#define SOR1_TIMING_CYA (1 << 27)
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#define CURSOR_ENABLE (1 << 16)
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#define SOR_ENABLE(x) (1 << (25 + (x)))
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#define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
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#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
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@ -521,7 +521,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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* is no possibility to perform the I2C mode configuration in the
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* HDMI path.
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*/
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err = tegra_dpaux_pad_config(dpaux, DPAUX_HYBRID_PADCTL_MODE_I2C);
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err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
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if (err < 0)
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return err;
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@ -639,6 +639,7 @@ static const struct dev_pm_ops tegra_dpaux_pm_ops = {
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};
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static const struct of_device_id tegra_dpaux_of_match[] = {
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{ .compatible = "nvidia,tegra194-dpaux", },
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{ .compatible = "nvidia,tegra186-dpaux", },
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{ .compatible = "nvidia,tegra210-dpaux", },
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{ .compatible = "nvidia,tegra124-dpaux", },
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@ -15,6 +15,10 @@
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
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#include <asm/dma-iommu.h>
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#endif
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#include "drm.h"
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#include "gem.h"
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@ -1068,6 +1072,14 @@ struct iommu_group *host1x_client_iommu_attach(struct host1x_client *client,
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}
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if (!shared || (shared && (group != tegra->group))) {
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#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
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if (client->dev->archdata.mapping) {
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struct dma_iommu_mapping *mapping =
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to_dma_iommu_mapping(client->dev);
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arm_iommu_detach_device(client->dev);
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arm_iommu_release_mapping(mapping);
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}
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#endif
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err = iommu_attach_group(tegra->domain, group);
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if (err < 0) {
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iommu_group_put(group);
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@ -1216,31 +1228,15 @@ static int host1x_drm_remove(struct host1x_device *dev)
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static int host1x_drm_suspend(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct tegra_drm *tegra = drm->dev_private;
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drm_kms_helper_poll_disable(drm);
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tegra_drm_fb_suspend(drm);
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tegra->state = drm_atomic_helper_suspend(drm);
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if (IS_ERR(tegra->state)) {
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tegra_drm_fb_resume(drm);
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drm_kms_helper_poll_enable(drm);
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return PTR_ERR(tegra->state);
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}
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return 0;
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return drm_mode_config_helper_suspend(drm);
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}
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static int host1x_drm_resume(struct device *dev)
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{
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struct drm_device *drm = dev_get_drvdata(dev);
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struct tegra_drm *tegra = drm->dev_private;
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drm_atomic_helper_resume(drm, tegra->state);
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tegra_drm_fb_resume(drm);
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drm_kms_helper_poll_enable(drm);
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return 0;
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return drm_mode_config_helper_resume(drm);
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}
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#endif
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@ -1275,6 +1271,9 @@ static const struct of_device_id host1x_drm_subdevs[] = {
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{ .compatible = "nvidia,tegra186-sor", },
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{ .compatible = "nvidia,tegra186-sor1", },
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{ .compatible = "nvidia,tegra186-vic", },
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{ .compatible = "nvidia,tegra194-display", },
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{ .compatible = "nvidia,tegra194-dc", },
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{ .compatible = "nvidia,tegra194-sor", },
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{ /* sentinel */ }
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};
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@ -60,8 +60,6 @@ struct tegra_drm {
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unsigned int pitch_align;
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struct tegra_display_hub *hub;
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struct drm_atomic_state *state;
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};
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struct tegra_drm_client;
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@ -186,8 +184,6 @@ int tegra_drm_fb_prepare(struct drm_device *drm);
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void tegra_drm_fb_free(struct drm_device *drm);
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int tegra_drm_fb_init(struct drm_device *drm);
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void tegra_drm_fb_exit(struct drm_device *drm);
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void tegra_drm_fb_suspend(struct drm_device *drm);
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void tegra_drm_fb_resume(struct drm_device *drm);
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extern struct platform_driver tegra_display_hub_driver;
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extern struct platform_driver tegra_dc_driver;
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@ -356,7 +356,7 @@ static void tegra_fbdev_exit(struct tegra_fbdev *fbdev)
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/* Undo the special mapping we made in fbdev probe. */
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if (bo && bo->pages) {
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vunmap(bo->vaddr);
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bo->vaddr = 0;
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bo->vaddr = NULL;
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}
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drm_framebuffer_remove(fbdev->fb);
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@ -412,25 +412,3 @@ void tegra_drm_fb_exit(struct drm_device *drm)
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tegra_fbdev_exit(tegra->fbdev);
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#endif
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}
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void tegra_drm_fb_suspend(struct drm_device *drm)
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{
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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struct tegra_drm *tegra = drm->dev_private;
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console_lock();
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drm_fb_helper_set_suspend(&tegra->fbdev->base, 1);
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console_unlock();
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#endif
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}
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void tegra_drm_fb_resume(struct drm_device *drm)
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{
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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struct tegra_drm *tegra = drm->dev_private;
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console_lock();
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drm_fb_helper_set_suspend(&tegra->fbdev->base, 0);
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console_unlock();
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#endif
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}
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@ -758,10 +758,12 @@ static int tegra_display_hub_probe(struct platform_device *pdev)
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return err;
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}
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hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
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if (IS_ERR(hub->clk_dsc)) {
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err = PTR_ERR(hub->clk_dsc);
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return err;
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if (hub->soc->supports_dsc) {
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hub->clk_dsc = devm_clk_get(&pdev->dev, "dsc");
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if (IS_ERR(hub->clk_dsc)) {
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err = PTR_ERR(hub->clk_dsc);
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return err;
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}
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}
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hub->clk_hub = devm_clk_get(&pdev->dev, "hub");
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@ -890,10 +892,19 @@ static const struct dev_pm_ops tegra_display_hub_pm_ops = {
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static const struct tegra_display_hub_soc tegra186_display_hub = {
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.num_wgrps = 6,
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.supports_dsc = true,
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};
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static const struct tegra_display_hub_soc tegra194_display_hub = {
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.num_wgrps = 6,
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.supports_dsc = false,
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};
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static const struct of_device_id tegra_display_hub_of_match[] = {
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{
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.compatible = "nvidia,tegra194-display",
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.data = &tegra194_display_hub
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}, {
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.compatible = "nvidia,tegra186-display",
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.data = &tegra186_display_hub
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}, {
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@ -38,6 +38,7 @@ to_tegra_shared_plane(struct drm_plane *plane)
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struct tegra_display_hub_soc {
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unsigned int num_wgrps;
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bool supports_dsc;
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};
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struct tegra_display_hub {
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@ -282,6 +282,85 @@ static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
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}
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};
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static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
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{
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.frequency = 54000000,
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.vcocap = 0,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 0xf,
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.tx_pu_value = 0,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x54,
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 75000000,
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.vcocap = 1,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 0xf,
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.tx_pu_value = 0,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x44,
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 150000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 15,
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.tx_pu_value = 0x66 /* 0 */,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x00, /* 0x34 */
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 300000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 15,
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.tx_pu_value = 64,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x34,
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.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
|
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
|
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}, {
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.frequency = 600000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
|
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.tmds_termadj = 12,
|
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.tx_pu_value = 96,
|
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.bg_temp_coef = 3,
|
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.bg_vref_level = 8,
|
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.avdd10_level = 4,
|
||||
.avdd14_level = 4,
|
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.sparepll = 0x34,
|
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.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
|
||||
.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
|
||||
}
|
||||
};
|
||||
|
||||
struct tegra_sor_regs {
|
||||
unsigned int head_state0;
|
||||
unsigned int head_state1;
|
||||
|
|
@ -2894,7 +2973,38 @@ static const struct tegra_sor_soc tegra186_sor1 = {
|
|||
.xbar_cfg = tegra124_sor_xbar_cfg,
|
||||
};
|
||||
|
||||
static const struct tegra_sor_regs tegra194_sor_regs = {
|
||||
.head_state0 = 0x151,
|
||||
.head_state1 = 0x155,
|
||||
.head_state2 = 0x159,
|
||||
.head_state3 = 0x15d,
|
||||
.head_state4 = 0x161,
|
||||
.head_state5 = 0x165,
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.pll0 = 0x169,
|
||||
.pll1 = 0x16a,
|
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.pll2 = 0x16b,
|
||||
.pll3 = 0x16c,
|
||||
.dp_padctl0 = 0x16e,
|
||||
.dp_padctl2 = 0x16f,
|
||||
};
|
||||
|
||||
static const struct tegra_sor_soc tegra194_sor = {
|
||||
.supports_edp = true,
|
||||
.supports_lvds = false,
|
||||
.supports_hdmi = true,
|
||||
.supports_dp = true,
|
||||
|
||||
.regs = &tegra194_sor_regs,
|
||||
.has_nvdisplay = true,
|
||||
|
||||
.num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
|
||||
.settings = tegra194_sor_hdmi_defaults,
|
||||
|
||||
.xbar_cfg = tegra210_sor_xbar_cfg,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_sor_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
|
||||
{ .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
|
||||
{ .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
|
||||
{ .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
|
||||
|
|
|
|||
|
|
@ -331,7 +331,7 @@ static const struct dev_pm_ops host1x_device_pm_ops = {
|
|||
struct bus_type host1x_bus_type = {
|
||||
.name = "host1x",
|
||||
.match = host1x_device_match,
|
||||
.dma_configure = host1x_dma_configure,
|
||||
.dma_configure = host1x_dma_configure,
|
||||
.pm = &host1x_device_pm_ops,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,10 @@
|
|||
#include <trace/events/host1x.h>
|
||||
#undef CREATE_TRACE_POINTS
|
||||
|
||||
#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
|
||||
#include <asm/dma-iommu.h>
|
||||
#endif
|
||||
|
||||
#include "bus.h"
|
||||
#include "channel.h"
|
||||
#include "debug.h"
|
||||
|
|
@ -217,7 +221,14 @@ static int host1x_probe(struct platform_device *pdev)
|
|||
dev_err(&pdev->dev, "failed to get reset: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
|
||||
if (host->dev->archdata.mapping) {
|
||||
struct dma_iommu_mapping *mapping =
|
||||
to_dma_iommu_mapping(host->dev);
|
||||
arm_iommu_detach_device(host->dev);
|
||||
arm_iommu_release_mapping(mapping);
|
||||
}
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
|
||||
goto skip_iommu;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue