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powerpc/32s: Reorganise DSI handler. 

The part decidated to handling hash_page() is fully unneeded for
processors not having real hash pages like the 603.

Lets enlarge the content of the feature fixup, and provide
an alternative which jumps directly instead of getting NIPs.

Also, in preparation of VMAP stacks, the end of DSI handler has moved
to later in the code as it won't fit anymore once VMAP stacks
are there.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/c31b22c91af8b011d0a4fd9e52ad6afb4b593f71.1576916812.git.christophe.leroy@c-s.fr
This commit is contained in:
Christophe Leroy 2019-12-21 08:32:36 +00:00 committed by Michael Ellerman
parent 99b229161f
commit 2e15001ea9
1 changed files with 19 additions and 16 deletions
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35
arch/powerpc/kernel/head_32.S
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@ -295,24 +295,20 @@ __secondary_hold_acknowledge:
DO_KVM 0x300 DO_KVM 0x300
DataAccess: DataAccess:
EXCEPTION_PROLOG EXCEPTION_PROLOG
mfspr r10,SPRN_DSISR get_and_save_dar_dsisr_on_stack r4, r5, r11
stw r10,_DSISR(r11)
#ifdef CONFIG_PPC_KUAP
andis. r0,r10,(DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
#else
andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
#endif
bne 1f /* if not, try to put a PTE */
mfspr r4,SPRN_DAR /* into the hash table */
rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
BEGIN_MMU_FTR_SECTION BEGIN_MMU_FTR_SECTION
#ifdef CONFIG_PPC_KUAP
andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
#else
andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
#endif
bne handle_page_fault_tramp_2 /* if not, try to put a PTE */
rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
bl hash_page bl hash_page
END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE) b handle_page_fault_tramp_1
1: lwz r5,_DSISR(r11) /* get DSISR value */ FTR_SECTION_ELSE
mfspr r4,SPRN_DAR b handle_page_fault_tramp_2
stw r4, _DAR(r11) ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
EXC_XFER_LITE(0x300, handle_page_fault)
/* Instruction access exception. */ /* Instruction access exception. */
. = 0x400 . = 0x400
@ -642,6 +638,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
. = 0x3000 . = 0x3000
handle_page_fault_tramp_1:
lwz r4, _DAR(r11)
lwz r5, _DSISR(r11)
/* fall through */
handle_page_fault_tramp_2:
EXC_XFER_LITE(0x300, handle_page_fault)
AltiVecUnavailable: AltiVecUnavailable:
EXCEPTION_PROLOG EXCEPTION_PROLOG
#ifdef CONFIG_ALTIVEC #ifdef CONFIG_ALTIVEC