mirror of https://gitee.com/openkylin/linux.git
coresight-etm4x: Adding CoreSight ETM4x driver
This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block to support HW assisted tracing on ARMv7 and ARMv8 architectures. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Pratik Patel
Greg Kroah-Hartman
parent
f5da7cb24b
commit
2e1cdfe184
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@ -0,0 +1,15 @@
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What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Enable/disable tracing on this specific trace entiry.
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Enabling a source implies the source has been configured
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properly and a sink has been identidifed for it. The path
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of coresight components linking the source to the sink is
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configured and managed automatically by the coresight framework.
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What: /sys/bus/coresight/devices/<memory_map>.etm/cpu
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) The CPU this tracing entity is associated with.
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@ -58,4 +58,15 @@ config CORESIGHT_SOURCE_ETM3X
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which allows tracing the instructions that a processor is executing
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This is primarily useful for instruction level tracing. Depending
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the ETM version data tracing may also be available.
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config CORESIGHT_SOURCE_ETM4X
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bool "CoreSight Embedded Trace Macrocell 4.x driver"
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depends on ARM64
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select CORESIGHT_LINKS_AND_SINKS
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help
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This driver provides support for the ETM4.x tracer module, tracing the
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instructions that a processor is executing. This is primarily useful
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for instruction level tracing. Depending on the implemented version
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data tracing may also be available.
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endif
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@ -9,3 +9,4 @@ obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o
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obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \
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coresight-replicator.o
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obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o
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obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o
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@ -0,0 +1,697 @@
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/sysfs.h>
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#include <linux/stat.h>
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/coresight.h>
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#include <linux/pm_wakeup.h>
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#include <linux/amba/bus.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <linux/pm_runtime.h>
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#include <asm/sections.h>
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#include "coresight-etm4x.h"
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static int boot_enable;
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module_param_named(boot_enable, boot_enable, int, S_IRUGO);
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/* The number of ETMv4 currently registered */
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static int etm4_count;
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static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
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static void etm4_os_unlock(void *info)
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{
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struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info;
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/* Writing any value to ETMOSLAR unlocks the trace registers */
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writel_relaxed(0x0, drvdata->base + TRCOSLAR);
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isb();
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}
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static bool etm4_arch_supported(u8 arch)
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{
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switch (arch) {
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case ETM_ARCH_V4:
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break;
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default:
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return false;
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}
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return true;
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}
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static int etm4_trace_id(struct coresight_device *csdev)
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{
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struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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unsigned long flags;
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int trace_id = -1;
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if (!drvdata->enable)
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return drvdata->trcid;
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pm_runtime_get_sync(drvdata->dev);
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spin_lock_irqsave(&drvdata->spinlock, flags);
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CS_UNLOCK(drvdata->base);
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trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
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trace_id &= ETM_TRACEID_MASK;
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CS_LOCK(drvdata->base);
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spin_unlock_irqrestore(&drvdata->spinlock, flags);
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pm_runtime_put(drvdata->dev);
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return trace_id;
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}
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static void etm4_enable_hw(void *info)
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{
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int i;
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struct etmv4_drvdata *drvdata = info;
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CS_UNLOCK(drvdata->base);
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etm4_os_unlock(drvdata);
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/* Disable the trace unit before programming trace registers */
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writel_relaxed(0, drvdata->base + TRCPRGCTLR);
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/* wait for TRCSTATR.IDLE to go up */
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if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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TRCSTATR);
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writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR);
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writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR);
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/* nothing specific implemented */
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writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
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writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R);
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writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R);
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writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR);
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writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR);
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writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR);
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writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR);
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writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR);
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writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
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writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR);
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writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR);
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writel_relaxed(drvdata->vissctlr,
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drvdata->base + TRCVISSCTLR);
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writel_relaxed(drvdata->vipcssctlr,
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drvdata->base + TRCVIPCSSCTLR);
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for (i = 0; i < drvdata->nrseqstate - 1; i++)
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writel_relaxed(drvdata->seq_ctrl[i],
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drvdata->base + TRCSEQEVRn(i));
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writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR);
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writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR);
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writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR);
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for (i = 0; i < drvdata->nr_cntr; i++) {
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writel_relaxed(drvdata->cntrldvr[i],
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drvdata->base + TRCCNTRLDVRn(i));
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writel_relaxed(drvdata->cntr_ctrl[i],
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drvdata->base + TRCCNTCTLRn(i));
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writel_relaxed(drvdata->cntr_val[i],
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drvdata->base + TRCCNTVRn(i));
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}
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for (i = 0; i < drvdata->nr_resource; i++)
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writel_relaxed(drvdata->res_ctrl[i],
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drvdata->base + TRCRSCTLRn(i));
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for (i = 0; i < drvdata->nr_ss_cmp; i++) {
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writel_relaxed(drvdata->ss_ctrl[i],
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drvdata->base + TRCSSCCRn(i));
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writel_relaxed(drvdata->ss_status[i],
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drvdata->base + TRCSSCSRn(i));
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writel_relaxed(drvdata->ss_pe_cmp[i],
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drvdata->base + TRCSSPCICRn(i));
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}
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for (i = 0; i < drvdata->nr_addr_cmp; i++) {
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writeq_relaxed(drvdata->addr_val[i],
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drvdata->base + TRCACVRn(i));
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writeq_relaxed(drvdata->addr_acc[i],
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drvdata->base + TRCACATRn(i));
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}
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for (i = 0; i < drvdata->numcidc; i++)
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writeq_relaxed(drvdata->ctxid_val[i],
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drvdata->base + TRCCIDCVRn(i));
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writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
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writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
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for (i = 0; i < drvdata->numvmidc; i++)
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writeq_relaxed(drvdata->vmid_val[i],
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drvdata->base + TRCVMIDCVRn(i));
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writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
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writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
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/* Enable the trace unit */
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writel_relaxed(1, drvdata->base + TRCPRGCTLR);
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/* wait for TRCSTATR.IDLE to go back down to '0' */
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if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
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dev_err(drvdata->dev,
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"timeout observed when probing at offset %#x\n",
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TRCSTATR);
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CS_LOCK(drvdata->base);
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dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
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}
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static int etm4_enable(struct coresight_device *csdev)
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{
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struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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int ret;
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pm_runtime_get_sync(drvdata->dev);
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spin_lock(&drvdata->spinlock);
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/*
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* Executing etm4_enable_hw on the cpu whose ETM is being enabled
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* ensures that register writes occur when cpu is powered.
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*/
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ret = smp_call_function_single(drvdata->cpu,
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etm4_enable_hw, drvdata, 1);
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if (ret)
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goto err;
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drvdata->enable = true;
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drvdata->sticky_enable = true;
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spin_unlock(&drvdata->spinlock);
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dev_info(drvdata->dev, "ETM tracing enabled\n");
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return 0;
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err:
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spin_unlock(&drvdata->spinlock);
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pm_runtime_put(drvdata->dev);
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return ret;
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}
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static void etm4_disable_hw(void *info)
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{
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u32 control;
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struct etmv4_drvdata *drvdata = info;
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CS_UNLOCK(drvdata->base);
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control = readl_relaxed(drvdata->base + TRCPRGCTLR);
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/* EN, bit[0] Trace unit enable bit */
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control &= ~0x1;
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/* make sure everything completes before disabling */
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mb();
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isb();
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writel_relaxed(control, drvdata->base + TRCPRGCTLR);
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CS_LOCK(drvdata->base);
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dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
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}
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static void etm4_disable(struct coresight_device *csdev)
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{
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struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
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/*
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* Taking hotplug lock here protects from clocks getting disabled
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* with tracing being left on (crash scenario) if user disable occurs
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* after cpu online mask indicates the cpu is offline but before the
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* DYING hotplug callback is serviced by the ETM driver.
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*/
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get_online_cpus();
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spin_lock(&drvdata->spinlock);
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/*
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* Executing etm4_disable_hw on the cpu whose ETM is being disabled
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* ensures that register writes occur when cpu is powered.
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*/
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smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
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drvdata->enable = false;
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spin_unlock(&drvdata->spinlock);
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put_online_cpus();
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pm_runtime_put(drvdata->dev);
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dev_info(drvdata->dev, "ETM tracing disabled\n");
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}
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static const struct coresight_ops_source etm4_source_ops = {
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.trace_id = etm4_trace_id,
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.enable = etm4_enable,
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.disable = etm4_disable,
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};
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static const struct coresight_ops etm4_cs_ops = {
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.source_ops = &etm4_source_ops,
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};
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static ssize_t cpu_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = drvdata->cpu;
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return scnprintf(buf, PAGE_SIZE, "%d\n", val);
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}
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static DEVICE_ATTR_RO(cpu);
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static struct attribute *coresight_etmv4_attrs[] = {
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&dev_attr_cpu.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(coresight_etmv4);
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static void etm4_init_arch_data(void *info)
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{
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u32 etmidr0;
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u32 etmidr1;
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u32 etmidr2;
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u32 etmidr3;
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u32 etmidr4;
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u32 etmidr5;
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struct etmv4_drvdata *drvdata = info;
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CS_UNLOCK(drvdata->base);
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/* find all capabilities of the tracing unit */
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etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
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/* INSTP0, bits[2:1] P0 tracing support field */
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if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
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drvdata->instrp0 = true;
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else
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drvdata->instrp0 = false;
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/* TRCBB, bit[5] Branch broadcast tracing support bit */
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if (BMVAL(etmidr0, 5, 5))
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drvdata->trcbb = true;
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else
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drvdata->trcbb = false;
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/* TRCCOND, bit[6] Conditional instruction tracing support bit */
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if (BMVAL(etmidr0, 6, 6))
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drvdata->trccond = true;
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else
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drvdata->trccond = false;
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/* TRCCCI, bit[7] Cycle counting instruction bit */
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if (BMVAL(etmidr0, 7, 7))
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drvdata->trccci = true;
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else
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drvdata->trccci = false;
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/* RETSTACK, bit[9] Return stack bit */
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if (BMVAL(etmidr0, 9, 9))
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drvdata->retstack = true;
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else
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drvdata->retstack = false;
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/* NUMEVENT, bits[11:10] Number of events field */
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drvdata->nr_event = BMVAL(etmidr0, 10, 11);
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/* QSUPP, bits[16:15] Q element support field */
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drvdata->q_support = BMVAL(etmidr0, 15, 16);
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/* TSSIZE, bits[28:24] Global timestamp size field */
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drvdata->ts_size = BMVAL(etmidr0, 24, 28);
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/* base architecture of trace unit */
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etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
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/*
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* TRCARCHMIN, bits[7:4] architecture the minor version number
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* TRCARCHMAJ, bits[11:8] architecture major versin number
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*/
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drvdata->arch = BMVAL(etmidr1, 4, 11);
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/* maximum size of resources */
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etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
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/* CIDSIZE, bits[9:5] Indicates the Context ID size */
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drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
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/* VMIDSIZE, bits[14:10] Indicates the VMID size */
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drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
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/* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
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drvdata->ccsize = BMVAL(etmidr2, 25, 28);
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etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
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/* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
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drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
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/* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
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drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
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/* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
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drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
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/*
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* TRCERR, bit[24] whether a trace unit can trace a
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* system error exception.
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*/
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if (BMVAL(etmidr3, 24, 24))
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drvdata->trc_error = true;
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else
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drvdata->trc_error = false;
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/* SYNCPR, bit[25] implementation has a fixed synchronization period? */
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if (BMVAL(etmidr3, 25, 25))
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drvdata->syncpr = true;
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else
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drvdata->syncpr = false;
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/* STALLCTL, bit[26] is stall control implemented? */
|
||||
if (BMVAL(etmidr3, 26, 26))
|
||||
drvdata->stallctl = true;
|
||||
else
|
||||
drvdata->stallctl = false;
|
||||
|
||||
/* SYSSTALL, bit[27] implementation can support stall control? */
|
||||
if (BMVAL(etmidr3, 27, 27))
|
||||
drvdata->sysstall = true;
|
||||
else
|
||||
drvdata->sysstall = false;
|
||||
|
||||
/* NUMPROC, bits[30:28] the number of PEs available for tracing */
|
||||
drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
|
||||
|
||||
/* NOOVERFLOW, bit[31] is trace overflow prevention supported */
|
||||
if (BMVAL(etmidr3, 31, 31))
|
||||
drvdata->nooverflow = true;
|
||||
else
|
||||
drvdata->nooverflow = false;
|
||||
|
||||
/* number of resources trace unit supports */
|
||||
etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
|
||||
/* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
|
||||
drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
|
||||
/* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
|
||||
drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
|
||||
/* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */
|
||||
drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
|
||||
/*
|
||||
* NUMSSCC, bits[23:20] the number of single-shot
|
||||
* comparator control for tracing
|
||||
*/
|
||||
drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
|
||||
/* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
|
||||
drvdata->numcidc = BMVAL(etmidr4, 24, 27);
|
||||
/* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
|
||||
drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
|
||||
|
||||
etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
|
||||
/* NUMEXTIN, bits[8:0] number of external inputs implemented */
|
||||
drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
|
||||
/* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
|
||||
drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
|
||||
/* ATBTRIG, bit[22] implementation can support ATB triggers? */
|
||||
if (BMVAL(etmidr5, 22, 22))
|
||||
drvdata->atbtrig = true;
|
||||
else
|
||||
drvdata->atbtrig = false;
|
||||
/*
|
||||
* LPOVERRIDE, bit[23] implementation supports
|
||||
* low-power state override
|
||||
*/
|
||||
if (BMVAL(etmidr5, 23, 23))
|
||||
drvdata->lpoverride = true;
|
||||
else
|
||||
drvdata->lpoverride = false;
|
||||
/* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
|
||||
drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
|
||||
/* NUMCNTR, bits[30:28] number of counters available for tracing */
|
||||
drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
|
||||
CS_LOCK(drvdata->base);
|
||||
}
|
||||
|
||||
static void etm4_init_default_data(struct etmv4_drvdata *drvdata)
|
||||
{
|
||||
int i;
|
||||
|
||||
drvdata->pe_sel = 0x0;
|
||||
drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID |
|
||||
ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK);
|
||||
|
||||
/* disable all events tracing */
|
||||
drvdata->eventctrl0 = 0x0;
|
||||
drvdata->eventctrl1 = 0x0;
|
||||
|
||||
/* disable stalling */
|
||||
drvdata->stall_ctrl = 0x0;
|
||||
|
||||
/* disable timestamp event */
|
||||
drvdata->ts_ctrl = 0x0;
|
||||
|
||||
/* enable trace synchronization every 4096 bytes for trace */
|
||||
if (drvdata->syncpr == false)
|
||||
drvdata->syncfreq = 0xC;
|
||||
|
||||
/*
|
||||
* enable viewInst to trace everything with start-stop logic in
|
||||
* started state
|
||||
*/
|
||||
drvdata->vinst_ctrl |= BIT(0);
|
||||
/* set initial state of start-stop logic */
|
||||
if (drvdata->nr_addr_cmp)
|
||||
drvdata->vinst_ctrl |= BIT(9);
|
||||
|
||||
/* no address range filtering for ViewInst */
|
||||
drvdata->viiectlr = 0x0;
|
||||
/* no start-stop filtering for ViewInst */
|
||||
drvdata->vissctlr = 0x0;
|
||||
|
||||
/* disable seq events */
|
||||
for (i = 0; i < drvdata->nrseqstate-1; i++)
|
||||
drvdata->seq_ctrl[i] = 0x0;
|
||||
drvdata->seq_rst = 0x0;
|
||||
drvdata->seq_state = 0x0;
|
||||
|
||||
/* disable external input events */
|
||||
drvdata->ext_inp = 0x0;
|
||||
|
||||
for (i = 0; i < drvdata->nr_cntr; i++) {
|
||||
drvdata->cntrldvr[i] = 0x0;
|
||||
drvdata->cntr_ctrl[i] = 0x0;
|
||||
drvdata->cntr_val[i] = 0x0;
|
||||
}
|
||||
|
||||
for (i = 2; i < drvdata->nr_resource * 2; i++)
|
||||
drvdata->res_ctrl[i] = 0x0;
|
||||
|
||||
for (i = 0; i < drvdata->nr_ss_cmp; i++) {
|
||||
drvdata->ss_ctrl[i] = 0x0;
|
||||
drvdata->ss_pe_cmp[i] = 0x0;
|
||||
}
|
||||
|
||||
if (drvdata->nr_addr_cmp >= 1) {
|
||||
drvdata->addr_val[0] = (unsigned long)_stext;
|
||||
drvdata->addr_val[1] = (unsigned long)_etext;
|
||||
drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
|
||||
drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
|
||||
}
|
||||
|
||||
for (i = 0; i < drvdata->numcidc; i++)
|
||||
drvdata->ctxid_val[i] = 0x0;
|
||||
drvdata->ctxid_mask0 = 0x0;
|
||||
drvdata->ctxid_mask1 = 0x0;
|
||||
|
||||
for (i = 0; i < drvdata->numvmidc; i++)
|
||||
drvdata->vmid_val[i] = 0x0;
|
||||
drvdata->vmid_mask0 = 0x0;
|
||||
drvdata->vmid_mask1 = 0x0;
|
||||
|
||||
/*
|
||||
* A trace ID value of 0 is invalid, so let's start at some
|
||||
* random value that fits in 7 bits. ETMv3.x has 0x10 so let's
|
||||
* start at 0x20.
|
||||
*/
|
||||
drvdata->trcid = 0x20 + drvdata->cpu;
|
||||
}
|
||||
|
||||
static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
|
||||
void *hcpu)
|
||||
{
|
||||
unsigned int cpu = (unsigned long)hcpu;
|
||||
|
||||
if (!etmdrvdata[cpu])
|
||||
goto out;
|
||||
|
||||
switch (action & (~CPU_TASKS_FROZEN)) {
|
||||
case CPU_STARTING:
|
||||
spin_lock(&etmdrvdata[cpu]->spinlock);
|
||||
if (!etmdrvdata[cpu]->os_unlock) {
|
||||
etm4_os_unlock(etmdrvdata[cpu]);
|
||||
etmdrvdata[cpu]->os_unlock = true;
|
||||
}
|
||||
|
||||
if (etmdrvdata[cpu]->enable)
|
||||
etm4_enable_hw(etmdrvdata[cpu]);
|
||||
spin_unlock(&etmdrvdata[cpu]->spinlock);
|
||||
break;
|
||||
|
||||
case CPU_ONLINE:
|
||||
if (etmdrvdata[cpu]->boot_enable &&
|
||||
!etmdrvdata[cpu]->sticky_enable)
|
||||
coresight_enable(etmdrvdata[cpu]->csdev);
|
||||
break;
|
||||
|
||||
case CPU_DYING:
|
||||
spin_lock(&etmdrvdata[cpu]->spinlock);
|
||||
if (etmdrvdata[cpu]->enable)
|
||||
etm4_disable_hw(etmdrvdata[cpu]);
|
||||
spin_unlock(&etmdrvdata[cpu]->spinlock);
|
||||
break;
|
||||
}
|
||||
out:
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block etm4_cpu_notifier = {
|
||||
.notifier_call = etm4_cpu_callback,
|
||||
};
|
||||
|
||||
static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
{
|
||||
int ret;
|
||||
void __iomem *base;
|
||||
struct device *dev = &adev->dev;
|
||||
struct coresight_platform_data *pdata = NULL;
|
||||
struct etmv4_drvdata *drvdata;
|
||||
struct resource *res = &adev->res;
|
||||
struct coresight_desc *desc;
|
||||
struct device_node *np = adev->dev.of_node;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
|
||||
if (!drvdata)
|
||||
return -ENOMEM;
|
||||
|
||||
if (np) {
|
||||
pdata = of_get_coresight_platform_data(dev, np);
|
||||
if (IS_ERR(pdata))
|
||||
return PTR_ERR(pdata);
|
||||
adev->dev.platform_data = pdata;
|
||||
}
|
||||
|
||||
drvdata->dev = &adev->dev;
|
||||
dev_set_drvdata(dev, drvdata);
|
||||
|
||||
/* Validity for the resource is already checked by the AMBA core */
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
drvdata->base = base;
|
||||
|
||||
spin_lock_init(&drvdata->spinlock);
|
||||
|
||||
drvdata->cpu = pdata ? pdata->cpu : 0;
|
||||
|
||||
get_online_cpus();
|
||||
etmdrvdata[drvdata->cpu] = drvdata;
|
||||
|
||||
if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1))
|
||||
drvdata->os_unlock = true;
|
||||
|
||||
if (smp_call_function_single(drvdata->cpu,
|
||||
etm4_init_arch_data, drvdata, 1))
|
||||
dev_err(dev, "ETM arch init failed\n");
|
||||
|
||||
if (!etm4_count++)
|
||||
register_hotcpu_notifier(&etm4_cpu_notifier);
|
||||
|
||||
put_online_cpus();
|
||||
|
||||
if (etm4_arch_supported(drvdata->arch) == false) {
|
||||
ret = -EINVAL;
|
||||
goto err_arch_supported;
|
||||
}
|
||||
etm4_init_default_data(drvdata);
|
||||
|
||||
pm_runtime_put(&adev->dev);
|
||||
|
||||
desc->type = CORESIGHT_DEV_TYPE_SOURCE;
|
||||
desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
|
||||
desc->ops = &etm4_cs_ops;
|
||||
desc->pdata = pdata;
|
||||
desc->dev = dev;
|
||||
desc->groups = coresight_etmv4_groups;
|
||||
drvdata->csdev = coresight_register(desc);
|
||||
if (IS_ERR(drvdata->csdev)) {
|
||||
ret = PTR_ERR(drvdata->csdev);
|
||||
goto err_coresight_register;
|
||||
}
|
||||
|
||||
dev_info(dev, "%s initialized\n", (char *)id->data);
|
||||
|
||||
if (boot_enable) {
|
||||
coresight_enable(drvdata->csdev);
|
||||
drvdata->boot_enable = true;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_arch_supported:
|
||||
pm_runtime_put(&adev->dev);
|
||||
err_coresight_register:
|
||||
if (--etm4_count == 0)
|
||||
unregister_hotcpu_notifier(&etm4_cpu_notifier);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int etm4_remove(struct amba_device *adev)
|
||||
{
|
||||
struct etmv4_drvdata *drvdata = amba_get_drvdata(adev);
|
||||
|
||||
coresight_unregister(drvdata->csdev);
|
||||
if (--etm4_count == 0)
|
||||
unregister_hotcpu_notifier(&etm4_cpu_notifier);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct amba_id etm4_ids[] = {
|
||||
{ /* ETM 4.0 - Qualcomm */
|
||||
.id = 0x0003b95d,
|
||||
.mask = 0x0003ffff,
|
||||
.data = "ETM 4.0",
|
||||
},
|
||||
{ /* ETM 4.0 - Juno board */
|
||||
.id = 0x000bb95e,
|
||||
.mask = 0x000fffff,
|
||||
.data = "ETM 4.0",
|
||||
},
|
||||
{ 0, 0},
|
||||
};
|
||||
|
||||
static struct amba_driver etm4x_driver = {
|
||||
.drv = {
|
||||
.name = "coresight-etm4x",
|
||||
},
|
||||
.probe = etm4_probe,
|
||||
.remove = etm4_remove,
|
||||
.id_table = etm4_ids,
|
||||
};
|
||||
|
||||
module_amba_driver(etm4x_driver);
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _CORESIGHT_CORESIGHT_ETM_H
|
||||
#define _CORESIGHT_CORESIGHT_ETM_H
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include "coresight-priv.h"
|
||||
|
||||
/*
|
||||
* Device registers:
|
||||
* 0x000 - 0x2FC: Trace registers
|
||||
* 0x300 - 0x314: Management registers
|
||||
* 0x318 - 0xEFC: Trace registers
|
||||
* 0xF00: Management registers
|
||||
* 0xFA0 - 0xFA4: Trace registers
|
||||
* 0xFA8 - 0xFFC: Management registers
|
||||
*/
|
||||
/* Trace registers (0x000-0x2FC) */
|
||||
/* Main control and configuration registers */
|
||||
#define TRCPRGCTLR 0x004
|
||||
#define TRCPROCSELR 0x008
|
||||
#define TRCSTATR 0x00C
|
||||
#define TRCCONFIGR 0x010
|
||||
#define TRCAUXCTLR 0x018
|
||||
#define TRCEVENTCTL0R 0x020
|
||||
#define TRCEVENTCTL1R 0x024
|
||||
#define TRCSTALLCTLR 0x02C
|
||||
#define TRCTSCTLR 0x030
|
||||
#define TRCSYNCPR 0x034
|
||||
#define TRCCCCTLR 0x038
|
||||
#define TRCBBCTLR 0x03C
|
||||
#define TRCTRACEIDR 0x040
|
||||
#define TRCQCTLR 0x044
|
||||
/* Filtering control registers */
|
||||
#define TRCVICTLR 0x080
|
||||
#define TRCVIIECTLR 0x084
|
||||
#define TRCVISSCTLR 0x088
|
||||
#define TRCVIPCSSCTLR 0x08C
|
||||
#define TRCVDCTLR 0x0A0
|
||||
#define TRCVDSACCTLR 0x0A4
|
||||
#define TRCVDARCCTLR 0x0A8
|
||||
/* Derived resources registers */
|
||||
#define TRCSEQEVRn(n) (0x100 + (n * 4))
|
||||
#define TRCSEQRSTEVR 0x118
|
||||
#define TRCSEQSTR 0x11C
|
||||
#define TRCEXTINSELR 0x120
|
||||
#define TRCCNTRLDVRn(n) (0x140 + (n * 4))
|
||||
#define TRCCNTCTLRn(n) (0x150 + (n * 4))
|
||||
#define TRCCNTVRn(n) (0x160 + (n * 4))
|
||||
/* ID registers */
|
||||
#define TRCIDR8 0x180
|
||||
#define TRCIDR9 0x184
|
||||
#define TRCIDR10 0x188
|
||||
#define TRCIDR11 0x18C
|
||||
#define TRCIDR12 0x190
|
||||
#define TRCIDR13 0x194
|
||||
#define TRCIMSPEC0 0x1C0
|
||||
#define TRCIMSPECn(n) (0x1C0 + (n * 4))
|
||||
#define TRCIDR0 0x1E0
|
||||
#define TRCIDR1 0x1E4
|
||||
#define TRCIDR2 0x1E8
|
||||
#define TRCIDR3 0x1EC
|
||||
#define TRCIDR4 0x1F0
|
||||
#define TRCIDR5 0x1F4
|
||||
#define TRCIDR6 0x1F8
|
||||
#define TRCIDR7 0x1FC
|
||||
/* Resource selection registers */
|
||||
#define TRCRSCTLRn(n) (0x200 + (n * 4))
|
||||
/* Single-shot comparator registers */
|
||||
#define TRCSSCCRn(n) (0x280 + (n * 4))
|
||||
#define TRCSSCSRn(n) (0x2A0 + (n * 4))
|
||||
#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
|
||||
/* Management registers (0x300-0x314) */
|
||||
#define TRCOSLAR 0x300
|
||||
#define TRCOSLSR 0x304
|
||||
#define TRCPDCR 0x310
|
||||
#define TRCPDSR 0x314
|
||||
/* Trace registers (0x318-0xEFC) */
|
||||
/* Comparator registers */
|
||||
#define TRCACVRn(n) (0x400 + (n * 8))
|
||||
#define TRCACATRn(n) (0x480 + (n * 8))
|
||||
#define TRCDVCVRn(n) (0x500 + (n * 16))
|
||||
#define TRCDVCMRn(n) (0x580 + (n * 16))
|
||||
#define TRCCIDCVRn(n) (0x600 + (n * 8))
|
||||
#define TRCVMIDCVRn(n) (0x640 + (n * 8))
|
||||
#define TRCCIDCCTLR0 0x680
|
||||
#define TRCCIDCCTLR1 0x684
|
||||
#define TRCVMIDCCTLR0 0x688
|
||||
#define TRCVMIDCCTLR1 0x68C
|
||||
/* Management register (0xF00) */
|
||||
/* Integration control registers */
|
||||
#define TRCITCTRL 0xF00
|
||||
/* Trace registers (0xFA0-0xFA4) */
|
||||
/* Claim tag registers */
|
||||
#define TRCCLAIMSET 0xFA0
|
||||
#define TRCCLAIMCLR 0xFA4
|
||||
/* Management registers (0xFA8-0xFFC) */
|
||||
#define TRCDEVAFF0 0xFA8
|
||||
#define TRCDEVAFF1 0xFAC
|
||||
#define TRCLAR 0xFB0
|
||||
#define TRCLSR 0xFB4
|
||||
#define TRCAUTHSTATUS 0xFB8
|
||||
#define TRCDEVARCH 0xFBC
|
||||
#define TRCDEVID 0xFC8
|
||||
#define TRCDEVTYPE 0xFCC
|
||||
#define TRCPIDR4 0xFD0
|
||||
#define TRCPIDR5 0xFD4
|
||||
#define TRCPIDR6 0xFD8
|
||||
#define TRCPIDR7 0xFDC
|
||||
#define TRCPIDR0 0xFE0
|
||||
#define TRCPIDR1 0xFE4
|
||||
#define TRCPIDR2 0xFE8
|
||||
#define TRCPIDR3 0xFEC
|
||||
#define TRCCIDR0 0xFF0
|
||||
#define TRCCIDR1 0xFF4
|
||||
#define TRCCIDR2 0xFF8
|
||||
#define TRCCIDR3 0xFFC
|
||||
|
||||
/* ETMv4 resources */
|
||||
#define ETM_MAX_NR_PE 8
|
||||
#define ETMv4_MAX_CNTR 4
|
||||
#define ETM_MAX_SEQ_STATES 4
|
||||
#define ETM_MAX_EXT_INP_SEL 4
|
||||
#define ETM_MAX_EXT_INP 256
|
||||
#define ETM_MAX_EXT_OUT 4
|
||||
#define ETM_MAX_SINGLE_ADDR_CMP 16
|
||||
#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
|
||||
#define ETM_MAX_DATA_VAL_CMP 8
|
||||
#define ETMv4_MAX_CTXID_CMP 8
|
||||
#define ETM_MAX_VMID_CMP 8
|
||||
#define ETM_MAX_PE_CMP 8
|
||||
#define ETM_MAX_RES_SEL 16
|
||||
#define ETM_MAX_SS_CMP 8
|
||||
|
||||
#define ETM_ARCH_V4 0x40
|
||||
#define ETMv4_SYNC_MASK 0x1F
|
||||
#define ETM_CYC_THRESHOLD_MASK 0xFFF
|
||||
#define ETMv4_EVENT_MASK 0xFF
|
||||
#define ETM_CNTR_MAX_VAL 0xFFFF
|
||||
#define ETM_TRACEID_MASK 0x3f
|
||||
|
||||
/* ETMv4 programming modes */
|
||||
#define ETM_MODE_EXCLUDE BIT(0)
|
||||
#define ETM_MODE_LOAD BIT(1)
|
||||
#define ETM_MODE_STORE BIT(2)
|
||||
#define ETM_MODE_LOAD_STORE BIT(3)
|
||||
#define ETM_MODE_BB BIT(4)
|
||||
#define ETMv4_MODE_CYCACC BIT(5)
|
||||
#define ETMv4_MODE_CTXID BIT(6)
|
||||
#define ETM_MODE_VMID BIT(7)
|
||||
#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
|
||||
#define ETMv4_MODE_TIMESTAMP BIT(11)
|
||||
#define ETM_MODE_RETURNSTACK BIT(12)
|
||||
#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
|
||||
#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
|
||||
#define ETM_MODE_DATA_TRACE_VAL BIT(16)
|
||||
#define ETM_MODE_ISTALL BIT(17)
|
||||
#define ETM_MODE_DSTALL BIT(18)
|
||||
#define ETM_MODE_ATB_TRIGGER BIT(19)
|
||||
#define ETM_MODE_LPOVERRIDE BIT(20)
|
||||
#define ETM_MODE_ISTALL_EN BIT(21)
|
||||
#define ETM_MODE_DSTALL_EN BIT(22)
|
||||
#define ETM_MODE_INSTPRIO BIT(23)
|
||||
#define ETM_MODE_NOOVERFLOW BIT(24)
|
||||
#define ETM_MODE_TRACE_RESET BIT(25)
|
||||
#define ETM_MODE_TRACE_ERR BIT(26)
|
||||
#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
|
||||
#define ETMv4_MODE_ALL 0xFFFFFFF
|
||||
|
||||
#define TRCSTATR_IDLE_BIT 0
|
||||
|
||||
/**
|
||||
* struct etm4_drvdata - specifics associated to an ETM component
|
||||
* @base: Memory mapped base address for this component.
|
||||
* @dev: The device entity associated to this component.
|
||||
* @csdev: Component vitals needed by the framework.
|
||||
* @spinlock: Only one at a time pls.
|
||||
* @cpu: The cpu this component is affined to.
|
||||
* @arch: ETM version number.
|
||||
* @enable: Is this ETM currently tracing.
|
||||
* @sticky_enable: true if ETM base configuration has been done.
|
||||
* @boot_enable:True if we should start tracing at boot time.
|
||||
* @os_unlock: True if access to management registers is allowed.
|
||||
* @nr_pe: The number of processing entity available for tracing.
|
||||
* @nr_pe_cmp: The number of processing entity comparator inputs that are
|
||||
* available for tracing.
|
||||
* @nr_addr_cmp:Number of pairs of address comparators available
|
||||
* as found in ETMIDR4 0-3.
|
||||
* @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
|
||||
* @nr_ext_inp: Number of external input.
|
||||
* @numcidc: Number of contextID comparators.
|
||||
* @numvmidc: Number of VMID comparators.
|
||||
* @nrseqstate: The number of sequencer states that are implemented.
|
||||
* @nr_event: Indicates how many events the trace unit support.
|
||||
* @nr_resource:The number of resource selection pairs available for tracing.
|
||||
* @nr_ss_cmp: Number of single-shot comparator controls that are available.
|
||||
* @mode: Controls various modes supported by this ETM.
|
||||
* @trcid: value of the current ID for this component.
|
||||
* @trcid_size: Indicates the trace ID width.
|
||||
* @instrp0: Tracing of load and store instructions
|
||||
* as P0 elements is supported.
|
||||
* @trccond: If the trace unit supports conditional
|
||||
* instruction tracing.
|
||||
* @retstack: Indicates if the implementation supports a return stack.
|
||||
* @trc_error: Whether a trace unit can trace a system
|
||||
* error exception.
|
||||
* @atbtrig: If the implementation can support ATB triggers
|
||||
* @lpoverride: If the implementation can support low-power state over.
|
||||
* @pe_sel: Controls which PE to trace.
|
||||
* @cfg: Controls the tracing options.
|
||||
* @eventctrl0: Controls the tracing of arbitrary events.
|
||||
* @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
|
||||
* @stallctl: If functionality that prevents trace unit buffer overflows
|
||||
* is available.
|
||||
* @sysstall: Does the system support stall control of the PE?
|
||||
* @nooverflow: Indicate if overflow prevention is supported.
|
||||
* @stall_ctrl: Enables trace unit functionality that prevents trace
|
||||
* unit buffer overflows.
|
||||
* @ts_size: Global timestamp size field.
|
||||
* @ts_ctrl: Controls the insertion of global timestamps in the
|
||||
* trace streams.
|
||||
* @syncpr: Indicates if an implementation has a fixed
|
||||
* synchronization period.
|
||||
* @syncfreq: Controls how often trace synchronization requests occur.
|
||||
* @trccci: Indicates if the trace unit supports cycle counting
|
||||
* for instruction.
|
||||
* @ccsize: Indicates the size of the cycle counter in bits.
|
||||
* @ccitmin: minimum value that can be programmed in
|
||||
* the TRCCCCTLR register.
|
||||
* @ccctlr: Sets the threshold value for cycle counting.
|
||||
* @trcbb: Indicates if the trace unit supports branch broadcast tracing.
|
||||
* @q_support: Q element support characteristics.
|
||||
* @vinst_ctrl: Controls instruction trace filtering.
|
||||
* @viiectlr: Set or read, the address range comparators.
|
||||
* @vissctlr: Set, or read, the single address comparators that control the
|
||||
* ViewInst start-stop logic.
|
||||
* @vipcssctlr: Set, or read, which PE comparator inputs can control the
|
||||
* ViewInst start-stop logic.
|
||||
* @seq_idx: Sequencor index selector.
|
||||
* @seq_ctrl: Control for the sequencer state transition control register.
|
||||
* @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
|
||||
* @seq_state: Set, or read the sequencer state.
|
||||
* @cntr_idx: Counter index seletor.
|
||||
* @cntrldvr: Sets or returns the reload count value for a counter.
|
||||
* @cntr_ctrl: Controls the operation of a counter.
|
||||
* @cntr_val: Sets or returns the value for a counter.
|
||||
* @res_idx: Resource index selector.
|
||||
* @res_ctrl: Controls the selection of the resources in the trace unit.
|
||||
* @ss_ctrl: Controls the corresponding single-shot comparator resource.
|
||||
* @ss_status: The status of the corresponding single-shot comparator.
|
||||
* @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
|
||||
* @addr_idx: Address comparator index selector.
|
||||
* @addr_val: Value for address comparator.
|
||||
* @addr_acc: Address comparator access type.
|
||||
* @addr_type: Current status of the comparator register.
|
||||
* @ctxid_idx: Context ID index selector.
|
||||
* @ctxid_size: Size of the context ID field to consider.
|
||||
* @ctxid_val: Value of the context ID comparator.
|
||||
* @ctxid_mask0:Context ID comparator mask for comparator 0-3.
|
||||
* @ctxid_mask1:Context ID comparator mask for comparator 4-7.
|
||||
* @vmid_idx: VM ID index selector.
|
||||
* @vmid_size: Size of the VM ID comparator to consider.
|
||||
* @vmid_val: Value of the VM ID comparator.
|
||||
* @vmid_mask0: VM ID comparator mask for comparator 0-3.
|
||||
* @vmid_mask1: VM ID comparator mask for comparator 4-7.
|
||||
* @s_ex_level: In secure state, indicates whether instruction tracing is
|
||||
* supported for the corresponding Exception level.
|
||||
* @ns_ex_level:In non-secure state, indicates whether instruction tracing is
|
||||
* supported for the corresponding Exception level.
|
||||
* @ext_inp: External input selection.
|
||||
*/
|
||||
struct etmv4_drvdata {
|
||||
void __iomem *base;
|
||||
struct device *dev;
|
||||
struct coresight_device *csdev;
|
||||
spinlock_t spinlock;
|
||||
int cpu;
|
||||
u8 arch;
|
||||
bool enable;
|
||||
bool sticky_enable;
|
||||
bool boot_enable;
|
||||
bool os_unlock;
|
||||
u8 nr_pe;
|
||||
u8 nr_pe_cmp;
|
||||
u8 nr_addr_cmp;
|
||||
u8 nr_cntr;
|
||||
u8 nr_ext_inp;
|
||||
u8 numcidc;
|
||||
u8 numvmidc;
|
||||
u8 nrseqstate;
|
||||
u8 nr_event;
|
||||
u8 nr_resource;
|
||||
u8 nr_ss_cmp;
|
||||
u32 mode;
|
||||
u8 trcid;
|
||||
u8 trcid_size;
|
||||
bool instrp0;
|
||||
bool trccond;
|
||||
bool retstack;
|
||||
bool trc_error;
|
||||
bool atbtrig;
|
||||
bool lpoverride;
|
||||
u32 pe_sel;
|
||||
u32 cfg;
|
||||
u32 eventctrl0;
|
||||
u32 eventctrl1;
|
||||
bool stallctl;
|
||||
bool sysstall;
|
||||
bool nooverflow;
|
||||
u32 stall_ctrl;
|
||||
u8 ts_size;
|
||||
u32 ts_ctrl;
|
||||
bool syncpr;
|
||||
u32 syncfreq;
|
||||
bool trccci;
|
||||
u8 ccsize;
|
||||
u8 ccitmin;
|
||||
u32 ccctlr;
|
||||
bool trcbb;
|
||||
u32 bb_ctrl;
|
||||
bool q_support;
|
||||
u32 vinst_ctrl;
|
||||
u32 viiectlr;
|
||||
u32 vissctlr;
|
||||
u32 vipcssctlr;
|
||||
u8 seq_idx;
|
||||
u32 seq_ctrl[ETM_MAX_SEQ_STATES];
|
||||
u32 seq_rst;
|
||||
u32 seq_state;
|
||||
u8 cntr_idx;
|
||||
u32 cntrldvr[ETMv4_MAX_CNTR];
|
||||
u32 cntr_ctrl[ETMv4_MAX_CNTR];
|
||||
u32 cntr_val[ETMv4_MAX_CNTR];
|
||||
u8 res_idx;
|
||||
u32 res_ctrl[ETM_MAX_RES_SEL];
|
||||
u32 ss_ctrl[ETM_MAX_SS_CMP];
|
||||
u32 ss_status[ETM_MAX_SS_CMP];
|
||||
u32 ss_pe_cmp[ETM_MAX_SS_CMP];
|
||||
u8 addr_idx;
|
||||
u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
|
||||
u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
|
||||
u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
|
||||
u8 ctxid_idx;
|
||||
u8 ctxid_size;
|
||||
u64 ctxid_val[ETMv4_MAX_CTXID_CMP];
|
||||
u32 ctxid_mask0;
|
||||
u32 ctxid_mask1;
|
||||
u8 vmid_idx;
|
||||
u8 vmid_size;
|
||||
u64 vmid_val[ETM_MAX_VMID_CMP];
|
||||
u32 vmid_mask0;
|
||||
u32 vmid_mask1;
|
||||
u8 s_ex_level;
|
||||
u8 ns_ex_level;
|
||||
u32 ext_inp;
|
||||
};
|
||||
|
||||
/* Address comparator access types */
|
||||
enum etm_addr_acctype {
|
||||
ETM_INSTR_ADDR,
|
||||
ETM_DATA_LOAD_ADDR,
|
||||
ETM_DATA_STORE_ADDR,
|
||||
ETM_DATA_LOAD_STORE_ADDR,
|
||||
};
|
||||
|
||||
/* Address comparator context types */
|
||||
enum etm_addr_ctxtype {
|
||||
ETM_CTX_NONE,
|
||||
ETM_CTX_CTXID,
|
||||
ETM_CTX_VMID,
|
||||
ETM_CTX_CTXID_VMID,
|
||||
};
|
||||
|
||||
enum etm_addr_type {
|
||||
ETM_ADDR_TYPE_NONE,
|
||||
ETM_ADDR_TYPE_SINGLE,
|
||||
ETM_ADDR_TYPE_RANGE,
|
||||
ETM_ADDR_TYPE_START,
|
||||
ETM_ADDR_TYPE_STOP,
|
||||
};
|
||||
#endif
|
||||
Loading…
Reference in New Issue