mirror of https://gitee.com/openkylin/linux.git
ARM: pm: convert samsung platforms to generic suspend/resume support
Tested-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
96c20015da
commit
2e2f3d3792
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@ -32,25 +32,13 @@
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* code after resume.
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*
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* entry:
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* r0 = pointer to the save block
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* r1 = v:p offset
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r4 - r12, lr }
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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stmia r0, { r4 - r13 } @ Save CP registers and SP
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@@ save our state to ram
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bl s3c_pm_cb_flushcache
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ldr r3, =resume_with_mmu
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bl cpu_suspend
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@@ call final suspend code
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ldr r0, =pm_cpu_sleep
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@ -61,18 +49,6 @@ ENTRY(s3c_cpu_save)
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resume_with_mmu:
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ldmfd sp!, { r4 - r12, pc } @ return, from sp from s3c_cpu_save
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.data
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/* the next bit is code, but it requires easy access to the
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* s3c_sleep_save_phys data before the MMU is switched on, so
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* we store the code that needs this variable in the .data where
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* the value can be written to (the .text segment is RO).
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*/
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* Sleep magic, the word before the resume entry point so that the
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* bootloader can check for a resumeable image. */
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@ -110,35 +86,4 @@ ENTRY(s3c_cpu_resume)
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orr r0, r0, #1 << 15 @ GPN15
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str r0, [ r3, #S3C64XX_GPNDAT ]
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#endif
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/* __v6_setup from arch/arm/mm/proc-v6.S, ensure that the caches
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* are thoroughly cleaned just in case the bootloader didn't do it
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* for us. */
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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@@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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@@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
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ldr r0, s3c_sleep_save_phys
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ldmia r0, { r4 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mov r0, #0 @ restore copro access controls
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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mcr p15, 0, r0, c7, c5, 4
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ldr r2, =resume_with_mmu
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mcr p15, 0, r9, c1, c0, 0 /* turn mmu back on */
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nop
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mov pc, r2 /* jump back */
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.end
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b cpu_resume
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@ -35,50 +35,24 @@
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/* s3c_cpu_save
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*
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* entry:
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* r0 = save address (virtual addr of s3c_sleep_save_phys)
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* r1 = v:p offset
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r3 - r12, lr }
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mrc p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mrc p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mrc p15, 0, r9, c1, c0, 0 @ Control register
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mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r11, c1, c0, 2 @ Co-processor access controls
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mrc p15, 0, r12, c10, c2, 0 @ Read PRRR
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mrc p15, 0, r3, c10, c2, 1 @ READ NMRR
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stmia r0, { r3 - r13 }
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bl s3c_pm_cb_flushcache
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ldr r3, =resume_with_mmu
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bl cpu_suspend
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ldr r0, =pm_cpu_sleep
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ldr r0, [ r0 ]
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mov pc, r0
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resume_with_mmu:
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/*
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* After MMU is turned on, restore the previous MMU table.
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*/
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ldr r9 , =(PAGE_OFFSET - PHYS_OFFSET)
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add r4, r4, r9
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str r12, [r4]
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ldmfd sp!, { r3 - r12, pc }
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.ltorg
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.data
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* s3c_cpu_resume entry.
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@ -96,75 +70,4 @@ s3c_sleep_save_phys:
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*/
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ENTRY(s3c_cpu_resume)
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mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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msr cpsr_c, r0
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I Cache
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ldr r0, s3c_sleep_save_phys @ address of restore block
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ldmia r0, { r3 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r8, c2, c0, 2 @ Translation Table Control
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mcr p15, 0, r7, c2, c0, 1 @ Translation Table BASE1
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mcr p15, 0, r6, c2, c0, 0 @ Translation Table BASE0
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mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ Invalidate I & D TLB
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mov r0, #0 @ restore copro access
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mcr p15, 0, r11, c1, c0, 2 @ Co-processor access
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mcr p15, 0, r0, c7, c5, 4
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mcr p15, 0, r12, c10, c2, 0 @ write PRRR
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mcr p15, 0, r3, c10, c2, 1 @ write NMRR
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/*
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* In Cortex-A8, when MMU is turned on, the pipeline is flushed.
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* And there are no valid entries in the MMU table at this point.
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* So before turning on the MMU, the MMU entry for the DRAM address
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* range is added. After the MMU is turned on, the other entries
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* in the MMU table will be restored.
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*/
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/* r6 = Translation Table BASE0 */
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mov r4, r6
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mov r4, r4, LSR #14
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mov r4, r4, LSL #14
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/* Load address for adding to MMU table list */
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ldr r11, =0xE010F000 @ INFORM0 reg.
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ldr r10, [r11, #0]
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mov r10, r10, LSR #18
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bic r10, r10, #0x3
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orr r4, r4, r10
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/* Calculate MMU table entry */
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mov r10, r10, LSL #18
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ldr r5, =0x40E
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orr r10, r10, r5
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/* Back up originally data */
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ldr r12, [r4]
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/* Add calculated MMU table entry into MMU table list */
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str r10, [r4]
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ldr r2, =resume_with_mmu
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mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc
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nop
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nop
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nop
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nop
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nop @ second-to-last before mmu
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mov pc, r2 @ go back to virtual address
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.ltorg
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b cpu_resume
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@ -44,23 +44,13 @@
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/* s3c_cpu_save
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*
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* entry:
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* r0 = save address (virtual addr of s3c_sleep_save_phys)
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* r1 = v:p offset
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*/
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ENTRY(s3c_cpu_save)
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stmfd sp!, { r4 - r12, lr }
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@@ store co-processor registers
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mrc p15, 0, r4, c13, c0, 0 @ PID
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mrc p15, 0, r5, c3, c0, 0 @ Domain ID
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mrc p15, 0, r6, c2, c0, 0 @ translation table base address
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mrc p15, 0, r7, c1, c0, 0 @ control register
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stmia r0, { r4 - r13 }
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@@ write our state back to RAM
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bl s3c_pm_cb_flushcache
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ldr r3, =resume_with_mmu
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bl cpu_suspend
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@@ jump to final code to send system to sleep
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ldr r0, =pm_cpu_sleep
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@ -76,20 +66,6 @@ resume_with_mmu:
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.ltorg
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@@ the next bits sit in the .data segment, even though they
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@@ happen to be code... the s3c_sleep_save_phys needs to be
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@@ accessed by the resume code before it can restore the MMU.
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@@ This means that the variable has to be close enough for the
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@@ code to read it... since the .text segment needs to be RO,
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@@ the data segment can be the only place to put this code.
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.data
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.global s3c_sleep_save_phys
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s3c_sleep_save_phys:
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.word 0
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/* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* s3c_cpu_resume entry.
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@ -100,10 +76,6 @@ s3c_sleep_save_phys:
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/* s3c_cpu_resume
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*
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* resume code entry for bootloader to call
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*
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* we must put this code here in the data segment as we have no
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* other way of restoring the stack pointer after sleep, and we
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* must not write to the code segment (code is read-only)
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*/
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ENTRY(s3c_cpu_resume)
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@ -134,25 +106,4 @@ ENTRY(s3c_cpu_resume)
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beq 1001b
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#endif /* CONFIG_DEBUG_RESUME */
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mov r1, #0
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mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
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mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
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ldr r0, s3c_sleep_save_phys @ address of restore block
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ldmia r0, { r4 - r13 }
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mcr p15, 0, r4, c13, c0, 0 @ PID
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ translation table base
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#ifdef CONFIG_DEBUG_RESUME
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mov r3, #'R'
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strb r3, [ r2, #S3C2410_UTXH ]
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#endif
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ldr r2, =resume_with_mmu
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mcr p15, 0, r7, c1, c0, 0 @ turn on MMU, etc
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nop @ second-to-last before mmu
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mov pc, r2 @ go back to virtual address
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.ltorg
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b cpu_resume
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@ -50,13 +50,11 @@ extern unsigned char pm_uart_udivslot; /* true to save UART UDIVSLOT */
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/* from sleep.S */
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extern int s3c_cpu_save(unsigned long *saveblk);
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extern int s3c_cpu_save(unsigned long *saveblk, long);
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extern void s3c_cpu_resume(void);
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extern void s3c2410_cpu_suspend(void);
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extern unsigned long s3c_sleep_save_phys;
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/* sleep save info */
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/**
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@ -179,13 +177,5 @@ extern void s3c_pm_restore_gpios(void);
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*/
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extern void s3c_pm_save_gpios(void);
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/**
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* s3c_pm_cb_flushcache - callback for assembly code
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*
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* Callback to issue flush_cache_all() as this call is
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* not a directly callable object.
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*/
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extern void s3c_pm_cb_flushcache(void);
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extern void s3c_pm_save_core(void);
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extern void s3c_pm_restore_core(void);
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@ -241,8 +241,6 @@ void (*pm_cpu_sleep)(void);
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static int s3c_pm_enter(suspend_state_t state)
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{
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static unsigned long regs_save[16];
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/* ensure the debug is initialised (if enabled) */
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s3c_pm_debug_init();
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@ -266,12 +264,6 @@ static int s3c_pm_enter(suspend_state_t state)
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return -EINVAL;
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}
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/* store the physical address of the register recovery block */
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s3c_sleep_save_phys = virt_to_phys(regs_save);
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S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
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/* save all necessary core registers not covered by the drivers */
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s3c_pm_save_gpios();
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@ -305,7 +297,7 @@ static int s3c_pm_enter(suspend_state_t state)
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* we resume as it saves its own register state and restores it
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* during the resume. */
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s3c_cpu_save(regs_save);
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s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
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/* restore the cpu state using the kernel's cpu init code. */
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@ -336,12 +328,6 @@ static int s3c_pm_enter(suspend_state_t state)
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return 0;
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}
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/* callback from assembly code */
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void s3c_pm_cb_flushcache(void)
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{
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flush_cache_all();
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}
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static int s3c_pm_prepare(void)
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{
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/* prepare check area if configured */
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