mirror of https://gitee.com/openkylin/linux.git
Linux 3.18-rc7
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJUe7l9AAoJEHm+PkMAQRiGkGcIAIryQ7NKn4IaxUtS807Lx4Ih obEnx7nNKZTXCZpD/7XQGHMMJyozMJR50PHZESJoHu4Luhv9h7EFRnyJ6MdqMlwn zla3zY0yRsHwPoJKcHbSE0CPHZz0WPQHj7IEbM+XJz2tMNJfbgTrezElmcCM4DRp c9ae+ggwZ2cyNYM0r2RSwSJ525WMh69f9dzSUE27fpvkllQgwqNs/jHYz8HNOEht FWcv5UhvzKjwJS3awULfOB3zH2QdFvVTrwAzd+kbV2Q6T6CaUoFRlhXeKUO6W2Jv pJM6oj8tMZUkdXEv7EQXT1kwEqC4DULTTTHs4tSF79O1ESmNfePiOwwBcwoM2nM= =kG1Y -----END PGP SIGNATURE----- Merge tag 'v3.18-rc7' into for-next ... for allowing more cleanups of hda_intel.c driver-caps where both upstream and for-next contain the changes.
This commit is contained in:
commit
2e3d4de1bd
|
@ -30,10 +30,6 @@ should only be used when a device has multiple interrupt parents.
|
|||
Example:
|
||||
interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
|
||||
|
||||
A device node may contain either "interrupts" or "interrupts-extended", but not
|
||||
both. If both properties are present, then the operating system should log an
|
||||
error and use only the data in "interrupts".
|
||||
|
||||
2) Interrupt controller nodes
|
||||
-----------------------------
|
||||
|
||||
|
|
|
@ -7,3 +7,14 @@ And for the interrupt mapping part:
|
|||
|
||||
Open Firmware Recommended Practice: Interrupt Mapping
|
||||
http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
|
||||
|
||||
Additionally to the properties specified in the above standards a host bridge
|
||||
driver implementation may support the following properties:
|
||||
|
||||
- linux,pci-domain:
|
||||
If present this property assigns a fixed PCI domain number to a host bridge,
|
||||
otherwise an unstable (across boots) unique number will be assigned.
|
||||
It is required to either not set this property at all or set it for all
|
||||
host bridges in the system, otherwise potentially conflicting domain numbers
|
||||
may be assigned to root buses behind different host bridges. The domain
|
||||
number for each host bridge in the system must be unique.
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
|
||||
TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number
|
||||
of subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
TZ1090's pin configuration nodes act as a container for an abitrary number of
|
||||
TZ1090's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Lantiq's pin configuration nodes act as a container for an abitrary number of
|
||||
Lantiq's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those group(s), and two pin configuration parameters:
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Lantiq's pin configuration nodes act as a container for an abitrary number of
|
||||
Lantiq's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those group(s), and two pin configuration parameters:
|
||||
|
|
|
@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an abitrary number of
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -13,7 +13,7 @@ Optional properties:
|
|||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes.
|
||||
SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
|
||||
Each of these subnodes represents some desired configuration for a group of pins.
|
||||
|
||||
Required subnode-properties:
|
||||
|
|
|
@ -32,7 +32,7 @@ Required properties:
|
|||
Please refer to pinctrl-bindings.txt in this directory for details of the common
|
||||
pinctrl bindings used by client devices.
|
||||
|
||||
SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each
|
||||
SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each
|
||||
of these subnodes represents muxing for a pin, a group, or a list of pins or
|
||||
groups.
|
||||
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -47,7 +47,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an abitrary number of
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -47,7 +47,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an abitrary number of
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the
|
|||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Qualcomm's pin configuration nodes act as a container for an abitrary number of
|
||||
Qualcomm's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
|
|
|
@ -34,6 +34,7 @@ chipidea Chipidea, Inc
|
|||
chrp Common Hardware Reference Platform
|
||||
chunghwa Chunghwa Picture Tubes Ltd.
|
||||
cirrus Cirrus Logic, Inc.
|
||||
cnm Chips&Media, Inc.
|
||||
cortina Cortina Systems, Inc.
|
||||
crystalfontz Crystalfontz America, Inc.
|
||||
dallas Maxim Integrated Products (formerly Dallas Semiconductor)
|
||||
|
@ -92,6 +93,7 @@ maxim Maxim Integrated Products
|
|||
mediatek MediaTek Inc.
|
||||
micrel Micrel Inc.
|
||||
microchip Microchip Technology Inc.
|
||||
micron Micron Technology Inc.
|
||||
mitsubishi Mitsubishi Electric Corporation
|
||||
mosaixtech Mosaix Technologies, Inc.
|
||||
moxa Moxa
|
||||
|
@ -127,6 +129,7 @@ renesas Renesas Electronics Corporation
|
|||
ricoh Ricoh Co. Ltd.
|
||||
rockchip Fuzhou Rockchip Electronics Co., Ltd
|
||||
samsung Samsung Semiconductor
|
||||
sandisk Sandisk Corporation
|
||||
sbs Smart Battery System
|
||||
schindler Schindler
|
||||
seagate Seagate Technology PLC
|
||||
|
@ -138,7 +141,7 @@ silergy Silergy Corp.
|
|||
sirf SiRF Technology, Inc.
|
||||
sitronix Sitronix Technology Corporation
|
||||
smsc Standard Microsystems Corporation
|
||||
snps Synopsys, Inc.
|
||||
snps Synopsys, Inc.
|
||||
solidrun SolidRun
|
||||
sony Sony Corporation
|
||||
spansion Spansion Inc.
|
||||
|
|
|
@ -64,7 +64,7 @@ is formed.
|
|||
At mount time, the two directories given as mount options "lowerdir" and
|
||||
"upperdir" are combined into a merged directory:
|
||||
|
||||
mount -t overlayfs overlayfs -olowerdir=/lower,upperdir=/upper,\
|
||||
mount -t overlay overlay -olowerdir=/lower,upperdir=/upper,\
|
||||
workdir=/work /merged
|
||||
|
||||
The "workdir" needs to be an empty directory on the same filesystem
|
||||
|
|
|
@ -136,7 +136,7 @@ SOF_TIMESTAMPING_OPT_ID:
|
|||
|
||||
This option is implemented only for transmit timestamps. There, the
|
||||
timestamp is always looped along with a struct sock_extended_err.
|
||||
The option modifies field ee_info to pass an id that is unique
|
||||
The option modifies field ee_data to pass an id that is unique
|
||||
among all possibly concurrently outstanding timestamp requests for
|
||||
that socket. In practice, it is a monotonically increasing u32
|
||||
(that wraps).
|
||||
|
|
|
@ -6888,11 +6888,12 @@ F: drivers/scsi/osd/
|
|||
F: include/scsi/osd_*
|
||||
F: fs/exofs/
|
||||
|
||||
OVERLAYFS FILESYSTEM
|
||||
OVERLAY FILESYSTEM
|
||||
M: Miklos Szeredi <miklos@szeredi.hu>
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
L: linux-unionfs@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/vfs.git
|
||||
S: Supported
|
||||
F: fs/overlayfs/*
|
||||
F: fs/overlayfs/
|
||||
F: Documentation/filesystems/overlayfs.txt
|
||||
|
||||
P54 WIRELESS DRIVER
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 18
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Diseased Newt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -624,4 +624,8 @@ &spi_1 {
|
|||
num-cs = <1>;
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
#include "cros-ec-keyboard.dtsi"
|
||||
|
|
|
@ -555,7 +555,7 @@ usb@12000000 {
|
|||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dwc3 {
|
||||
usbdrd_dwc3: dwc3 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x12000000 0x10000>;
|
||||
interrupts = <0 72 0>;
|
||||
|
|
|
@ -433,7 +433,7 @@ mstp1_clks: mstp1_clks@e6150134 {
|
|||
clocks = <&cpg_clocks R8A7740_CLK_S>,
|
||||
<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>,
|
||||
<&sub_clk>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
|
||||
<&cpg_clocks R8A7740_CLK_B>;
|
||||
#clock-cells = <1>;
|
||||
renesas,clock-indices = <
|
||||
|
|
|
@ -666,9 +666,9 @@ sd2_clk: sd2_clk@e6150078 {
|
|||
#clock-cells = <0>;
|
||||
clock-output-names = "sd2";
|
||||
};
|
||||
sd3_clk: sd3_clk@e615007c {
|
||||
sd3_clk: sd3_clk@e615026c {
|
||||
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
|
||||
reg = <0 0xe615007c 0 4>;
|
||||
reg = <0 0xe615026c 0 4>;
|
||||
clocks = <&pll1_div2_clk>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "sd3";
|
||||
|
|
|
@ -361,6 +361,10 @@ dma: dma-controller@01c02000 {
|
|||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
/* DMA controller requires AHB1 clocked from PLL6 */
|
||||
assigned-clocks = <&ahb1_mux>;
|
||||
assigned-clock-parents = <&pll6>;
|
||||
};
|
||||
|
||||
mmc0: mmc@01c0f000 {
|
||||
|
|
|
@ -15,6 +15,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65913@58";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -15,6 +15,10 @@ chosen {
|
|||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
|
@ -916,8 +920,6 @@ vddio_sdmmc3: ldo9 {
|
|||
regulator-name = "vddio-sdmmc3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb {
|
||||
|
@ -962,7 +964,7 @@ pmc@7000e400 {
|
|||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vddio_sdmmc3>;
|
||||
vqmmc-supply = <&vddio_sdmmc3>;
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
@ -971,7 +973,6 @@ sdhci@78000400 {
|
|||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
@ -15,6 +15,10 @@ chosen {
|
|||
linux,initrd-end = <0x82800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
firmware {
|
||||
trusted-foundations {
|
||||
compatible = "tlm,trusted-foundations";
|
||||
|
@ -240,7 +244,6 @@ pmc@7000e400 {
|
|||
sdhci@78000600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&vdd_1v8>;
|
||||
non-removable;
|
||||
};
|
||||
|
||||
|
|
|
@ -9,13 +9,6 @@ / {
|
|||
compatible = "nvidia,tegra114";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra114-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00028000>;
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@0,7000d000/pmic@40";
|
||||
rtc1 = "/rtc@0,7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -286,7 +286,7 @@ pinmux: pinmux@0,70000868 {
|
|||
* the APB DMA based serial driver, the comptible is
|
||||
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
|
||||
*/
|
||||
serial@0,70006000 {
|
||||
uarta: serial@0,70006000 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006000 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -299,7 +299,7 @@ serial@0,70006000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006040 {
|
||||
uartb: serial@0,70006040 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006040 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -312,7 +312,7 @@ serial@0,70006040 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006200 {
|
||||
uartc: serial@0,70006200 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006200 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
@ -325,7 +325,7 @@ serial@0,70006200 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006300 {
|
||||
uartd: serial@0,70006300 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006300 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -6,6 +6,11 @@ / {
|
|||
model = "Toradex Colibri T20 512MB on Iris";
|
||||
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
|
|
@ -6,6 +6,10 @@ / {
|
|||
model = "Avionic Design Medcom-Wide board";
|
||||
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
aliases {
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -10,6 +10,8 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -7,6 +7,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000c500/rtc@56";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps6586x@34";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uartd;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/max8907@3c";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -9,14 +9,6 @@ / {
|
|||
compatible = "nvidia,tegra20";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
|
|
|
@ -11,6 +11,10 @@ aliases {
|
|||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
|
|
|
@ -9,6 +9,7 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -30,6 +30,8 @@ / {
|
|||
aliases {
|
||||
rtc0 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc1 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartc;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
|
|
@ -10,6 +10,9 @@ aliases {
|
|||
rtc0 = "/i2c@7000c000/rtc@68";
|
||||
rtc1 = "/i2c@7000d000/tps65911@2d";
|
||||
rtc2 = "/rtc@7000e000";
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartd;
|
||||
};
|
||||
|
||||
host1x@50000000 {
|
||||
|
|
|
@ -9,14 +9,6 @@ / {
|
|||
compatible = "nvidia,tegra30";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uarta;
|
||||
serial1 = &uartb;
|
||||
serial2 = &uartc;
|
||||
serial3 = &uartd;
|
||||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
pcie-controller@00003000 {
|
||||
compatible = "nvidia,tegra30-pcie";
|
||||
device_type = "pci";
|
||||
|
|
|
@ -142,11 +142,13 @@ CONFIG_MMC_DW_IDMAC=y
|
|||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_MAX77802=y
|
||||
CONFIG_RTC_DRV_S5M=y
|
||||
CONFIG_RTC_DRV_S3C=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_COMMON_CLK_MAX77686=y
|
||||
CONFIG_COMMON_CLK_MAX77802=y
|
||||
CONFIG_COMMON_CLK_S2MPS11=y
|
||||
CONFIG_EXYNOS_IOMMU=y
|
||||
CONFIG_IIO=y
|
||||
|
|
|
@ -217,6 +217,7 @@ CONFIG_I2C_CADENCE=y
|
|||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_EXYNOS5=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_S3C2410=y
|
||||
CONFIG_I2C_SIRF=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_ST=y
|
||||
|
|
|
@ -44,16 +44,6 @@ struct cpu_context_save {
|
|||
__u32 extra[2]; /* Xscale 'acc' register, etc */
|
||||
};
|
||||
|
||||
struct arm_restart_block {
|
||||
union {
|
||||
/* For user cache flushing */
|
||||
struct {
|
||||
unsigned long start;
|
||||
unsigned long end;
|
||||
} cache;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* low level task data that entry.S needs immediate access to.
|
||||
* __switch_to() assumes cpu_context follows immediately after cpu_domain.
|
||||
|
@ -79,7 +69,6 @@ struct thread_info {
|
|||
unsigned long thumbee_state; /* ThumbEE Handler Base register */
|
||||
#endif
|
||||
struct restart_block restart_block;
|
||||
struct arm_restart_block arm_restart_block;
|
||||
};
|
||||
|
||||
#define INIT_THREAD_INFO(tsk) \
|
||||
|
|
|
@ -533,8 +533,6 @@ static int bad_syscall(int n, struct pt_regs *regs)
|
|||
return regs->ARM_r0;
|
||||
}
|
||||
|
||||
static long do_cache_op_restart(struct restart_block *);
|
||||
|
||||
static inline int
|
||||
__do_cache_op(unsigned long start, unsigned long end)
|
||||
{
|
||||
|
@ -543,24 +541,8 @@ __do_cache_op(unsigned long start, unsigned long end)
|
|||
do {
|
||||
unsigned long chunk = min(PAGE_SIZE, end - start);
|
||||
|
||||
if (signal_pending(current)) {
|
||||
struct thread_info *ti = current_thread_info();
|
||||
|
||||
ti->restart_block = (struct restart_block) {
|
||||
.fn = do_cache_op_restart,
|
||||
};
|
||||
|
||||
ti->arm_restart_block = (struct arm_restart_block) {
|
||||
{
|
||||
.cache = {
|
||||
.start = start,
|
||||
.end = end,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
return -ERESTART_RESTARTBLOCK;
|
||||
}
|
||||
if (fatal_signal_pending(current))
|
||||
return 0;
|
||||
|
||||
ret = flush_cache_user_range(start, start + chunk);
|
||||
if (ret)
|
||||
|
@ -573,15 +555,6 @@ __do_cache_op(unsigned long start, unsigned long end)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static long do_cache_op_restart(struct restart_block *unused)
|
||||
{
|
||||
struct arm_restart_block *restart_block;
|
||||
|
||||
restart_block = ¤t_thread_info()->arm_restart_block;
|
||||
return __do_cache_op(restart_block->cache.start,
|
||||
restart_block->cache.end);
|
||||
}
|
||||
|
||||
static inline int
|
||||
do_cache_op(unsigned long start, unsigned long end, int flags)
|
||||
{
|
||||
|
|
|
@ -197,7 +197,8 @@ static void unmap_range(struct kvm *kvm, pgd_t *pgdp,
|
|||
pgd = pgdp + pgd_index(addr);
|
||||
do {
|
||||
next = kvm_pgd_addr_end(addr, end);
|
||||
unmap_puds(kvm, pgd, addr, next);
|
||||
if (!pgd_none(*pgd))
|
||||
unmap_puds(kvm, pgd, addr, next);
|
||||
} while (pgd++, addr = next, addr != end);
|
||||
}
|
||||
|
||||
|
@ -834,6 +835,11 @@ static bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
|||
return kvm_vcpu_dabt_iswrite(vcpu);
|
||||
}
|
||||
|
||||
static bool kvm_is_device_pfn(unsigned long pfn)
|
||||
{
|
||||
return !pfn_valid(pfn);
|
||||
}
|
||||
|
||||
static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
||||
struct kvm_memory_slot *memslot, unsigned long hva,
|
||||
unsigned long fault_status)
|
||||
|
@ -904,7 +910,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
|
|||
if (is_error_pfn(pfn))
|
||||
return -EFAULT;
|
||||
|
||||
if (kvm_is_mmio_pfn(pfn))
|
||||
if (kvm_is_device_pfn(pfn))
|
||||
mem_type = PAGE_S2_DEVICE;
|
||||
|
||||
spin_lock(&kvm->mmu_lock);
|
||||
|
|
|
@ -400,6 +400,8 @@ int __init coherency_init(void)
|
|||
type == COHERENCY_FABRIC_TYPE_ARMADA_380)
|
||||
armada_375_380_coherency_init(np);
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -455,7 +455,7 @@ enum {
|
|||
MSTP128, MSTP127, MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
||||
MSTP230,
|
||||
MSTP230, MSTP229,
|
||||
MSTP222,
|
||||
MSTP218, MSTP217, MSTP216, MSTP214,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
|
@ -474,11 +474,12 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S], SMSTPCR1, 27, 0), /* CEU20 */
|
||||
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div4_clks[DIV4_HPP], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
|
||||
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
|
||||
[MSTP229] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 29, 0), /* INTCA */
|
||||
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
|
||||
[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
|
||||
[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
|
||||
|
@ -575,6 +576,10 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("e6cd0000.serial", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.0", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.1", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.2", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("renesas_intc_irqpin.3", &mstp_clks[MSTP229]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
CLKDEV_DEV_ID("e6cc0000.serial", &mstp_clks[MSTP230]),
|
||||
|
||||
|
|
|
@ -68,7 +68,7 @@
|
|||
|
||||
#define SDCKCR 0xE6150074
|
||||
#define SD2CKCR 0xE6150078
|
||||
#define SD3CKCR 0xE615007C
|
||||
#define SD3CKCR 0xE615026C
|
||||
#define MMC0CKCR 0xE6150240
|
||||
#define MMC1CKCR 0xE6150244
|
||||
#define SSPCKCR 0xE6150248
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c/i2c-sh_mobile.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_dma.h>
|
||||
|
@ -192,11 +193,18 @@ static struct resource i2c4_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct i2c_sh_mobile_platform_data i2c_platform_data = {
|
||||
.clks_per_count = 2,
|
||||
};
|
||||
|
||||
static struct platform_device i2c0_device = {
|
||||
.name = "i2c-sh_mobile",
|
||||
.id = 0,
|
||||
.resource = i2c0_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c0_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c1_device = {
|
||||
|
@ -204,6 +212,9 @@ static struct platform_device i2c1_device = {
|
|||
.id = 1,
|
||||
.resource = i2c1_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c1_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c2_device = {
|
||||
|
@ -211,6 +222,9 @@ static struct platform_device i2c2_device = {
|
|||
.id = 2,
|
||||
.resource = i2c2_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c2_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c3_device = {
|
||||
|
@ -218,6 +232,9 @@ static struct platform_device i2c3_device = {
|
|||
.id = 3,
|
||||
.resource = i2c3_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c3_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c4_device = {
|
||||
|
@ -225,6 +242,9 @@ static struct platform_device i2c4_device = {
|
|||
.id = 4,
|
||||
.resource = i2c4_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c4_resources),
|
||||
.dev = {
|
||||
.platform_data = &i2c_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
|
||||
|
|
|
@ -99,42 +99,42 @@ static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
|
|||
|
||||
static void tegra_mask(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_CLR);
|
||||
}
|
||||
|
||||
static void tegra_unmask(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IER_SET);
|
||||
}
|
||||
|
||||
static void tegra_ack(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
}
|
||||
|
||||
static void tegra_eoi(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_CLR);
|
||||
}
|
||||
|
||||
static int tegra_retrigger(struct irq_data *d)
|
||||
{
|
||||
if (d->irq < FIRST_LEGACY_IRQ)
|
||||
if (d->hwirq < FIRST_LEGACY_IRQ)
|
||||
return 0;
|
||||
|
||||
tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
|
||||
tegra_irq_write_mask(d->hwirq, ICTLR_CPU_IEP_FIR_SET);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
@ -142,7 +142,7 @@ static int tegra_retrigger(struct irq_data *d)
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int tegra_set_wake(struct irq_data *d, unsigned int enable)
|
||||
{
|
||||
u32 irq = d->irq;
|
||||
u32 irq = d->hwirq;
|
||||
u32 index, mask;
|
||||
|
||||
if (irq < FIRST_LEGACY_IRQ ||
|
||||
|
|
|
@ -270,7 +270,6 @@ __v7_pj4b_setup:
|
|||
/* Auxiliary Debug Modes Control 1 Register */
|
||||
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
|
||||
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
|
||||
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
|
||||
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
|
||||
|
||||
/* Auxiliary Debug Modes Control 2 Register */
|
||||
|
@ -293,7 +292,6 @@ __v7_pj4b_setup:
|
|||
/* Auxiliary Debug Modes Control 1 Register */
|
||||
mrc p15, 1, r0, c15, c1, 1
|
||||
orr r0, r0, #PJ4B_CLEAN_LINE
|
||||
orr r0, r0, #PJ4B_BCK_OFF_STREX
|
||||
orr r0, r0, #PJ4B_INTER_PARITY
|
||||
bic r0, r0, #PJ4B_STATIC_BP
|
||||
mcr p15, 1, r0, c15, c1, 1
|
||||
|
|
|
@ -535,7 +535,7 @@ ENTRY(cpu_xscale_do_suspend)
|
|||
mrc p15, 0, r5, c15, c1, 0 @ CP access reg
|
||||
mrc p15, 0, r6, c13, c0, 0 @ PID
|
||||
mrc p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mrc p15, 0, r9, c1, c0, 0 @ control reg
|
||||
bic r4, r4, #2 @ clear frequency change bit
|
||||
stmia r0, {r4 - r9} @ store cp regs
|
||||
|
@ -552,7 +552,7 @@ ENTRY(cpu_xscale_do_resume)
|
|||
mcr p15, 0, r6, c13, c0, 0 @ PID
|
||||
mcr p15, 0, r7, c3, c0, 0 @ domain ID
|
||||
mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
|
||||
mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
|
||||
mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
|
||||
mov r0, r9 @ control register
|
||||
b cpu_resume_mmu
|
||||
ENDPROC(cpu_xscale_do_resume)
|
||||
|
|
|
@ -424,6 +424,11 @@ static const struct sys_reg_desc sys_reg_descs[] = {
|
|||
/* VBAR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
|
||||
NULL, reset_val, VBAR_EL1, 0 },
|
||||
|
||||
/* ICC_SRE_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
|
||||
trap_raz_wi },
|
||||
|
||||
/* CONTEXTIDR_EL1 */
|
||||
{ Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
|
||||
access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
|
||||
|
@ -690,6 +695,10 @@ static const struct sys_reg_desc cp15_regs[] = {
|
|||
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
|
||||
{ Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
|
||||
{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
|
||||
|
||||
/* ICC_SRE */
|
||||
{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
|
||||
|
||||
{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
|
||||
};
|
||||
|
||||
|
|
|
@ -1563,7 +1563,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
|
|||
|
||||
for (i = 0; i < npages; i++) {
|
||||
pfn = gfn_to_pfn(kvm, base_gfn + i);
|
||||
if (!kvm_is_mmio_pfn(pfn)) {
|
||||
if (!kvm_is_reserved_pfn(pfn)) {
|
||||
kvm_set_pmt_entry(kvm, base_gfn + i,
|
||||
pfn << PAGE_SHIFT,
|
||||
_PAGE_AR_RWX | _PAGE_MA_WB);
|
||||
|
|
|
@ -2101,9 +2101,17 @@ config 64BIT_PHYS_ADDR
|
|||
config ARCH_PHYS_ADDR_T_64BIT
|
||||
def_bool 64BIT_PHYS_ADDR
|
||||
|
||||
choice
|
||||
prompt "SmartMIPS or microMIPS ASE support"
|
||||
|
||||
config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS
|
||||
bool "None"
|
||||
help
|
||||
Select this if you want neither microMIPS nor SmartMIPS support
|
||||
|
||||
config CPU_HAS_SMARTMIPS
|
||||
depends on SYS_SUPPORTS_SMARTMIPS
|
||||
bool "Support for the SmartMIPS ASE"
|
||||
bool "SmartMIPS"
|
||||
help
|
||||
SmartMIPS is a extension of the MIPS32 architecture aimed at
|
||||
increased security at both hardware and software level for
|
||||
|
@ -2115,11 +2123,13 @@ config CPU_HAS_SMARTMIPS
|
|||
|
||||
config CPU_MICROMIPS
|
||||
depends on SYS_SUPPORTS_MICROMIPS
|
||||
bool "Build kernel using microMIPS ISA"
|
||||
bool "microMIPS"
|
||||
help
|
||||
When this option is enabled the kernel will be built using the
|
||||
microMIPS ISA
|
||||
|
||||
endchoice
|
||||
|
||||
config CPU_HAS_MSA
|
||||
bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"
|
||||
depends on CPU_SUPPORTS_MSA
|
||||
|
|
|
@ -20,9 +20,15 @@
|
|||
#define WORD_INSN ".word"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
#define NOP_INSN "nop32"
|
||||
#else
|
||||
#define NOP_INSN "nop"
|
||||
#endif
|
||||
|
||||
static __always_inline bool arch_static_branch(struct static_key *key)
|
||||
{
|
||||
asm_volatile_goto("1:\tnop\n\t"
|
||||
asm_volatile_goto("1:\t" NOP_INSN "\n\t"
|
||||
"nop\n\t"
|
||||
".pushsection __jump_table, \"aw\"\n\t"
|
||||
WORD_INSN " 1b, %l[l_yes], %0\n\t"
|
||||
|
|
|
@ -41,10 +41,8 @@
|
|||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_prefetch 0
|
||||
|
|
|
@ -661,6 +661,8 @@
|
|||
#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
|
||||
/* proAptiv FTLB on/off bit */
|
||||
#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
|
||||
/* FTLB probability bits */
|
||||
#define MIPS_CONF6_FTLBP_SHIFT (16)
|
||||
|
||||
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
|
||||
|
||||
|
|
|
@ -257,7 +257,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
|
|||
*/
|
||||
static inline void protected_writeback_dcache_line(unsigned long addr)
|
||||
{
|
||||
#ifdef CONFIG_EVA
|
||||
protected_cachee_op(Hit_Writeback_Inv_D, addr);
|
||||
#else
|
||||
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void protected_writeback_scache_line(unsigned long addr)
|
||||
|
|
|
@ -301,7 +301,8 @@ do { \
|
|||
__get_kernel_common((x), size, __gu_ptr); \
|
||||
else \
|
||||
__get_user_common((x), size, __gu_ptr); \
|
||||
} \
|
||||
} else \
|
||||
(x) = 0; \
|
||||
\
|
||||
__gu_err; \
|
||||
})
|
||||
|
@ -316,6 +317,7 @@ do { \
|
|||
" .insn \n" \
|
||||
" .section .fixup,\"ax\" \n" \
|
||||
"3: li %0, %4 \n" \
|
||||
" move %1, $0 \n" \
|
||||
" j 2b \n" \
|
||||
" .previous \n" \
|
||||
" .section __ex_table,\"a\" \n" \
|
||||
|
@ -630,6 +632,7 @@ do { \
|
|||
" .insn \n" \
|
||||
" .section .fixup,\"ax\" \n" \
|
||||
"3: li %0, %4 \n" \
|
||||
" move %1, $0 \n" \
|
||||
" j 2b \n" \
|
||||
" .previous \n" \
|
||||
" .section __ex_table,\"a\" \n" \
|
||||
|
@ -773,10 +776,11 @@ extern void __put_user_unaligned_unknown(void);
|
|||
"jal\t" #destination "\n\t"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
|
||||
#define DADDI_SCRATCH "$0"
|
||||
#else
|
||||
#if defined(CONFIG_CPU_DADDI_WORKAROUNDS) || (defined(CONFIG_EVA) && \
|
||||
defined(CONFIG_CPU_HAS_PREFETCH))
|
||||
#define DADDI_SCRATCH "$3"
|
||||
#else
|
||||
#define DADDI_SCRATCH "$0"
|
||||
#endif
|
||||
|
||||
extern size_t __copy_user(void *__to, const void *__from, size_t __n);
|
||||
|
@ -1418,7 +1422,7 @@ static inline long __strnlen_user(const char __user *s, long n)
|
|||
}
|
||||
|
||||
/*
|
||||
* strlen_user: - Get the size of a string in user space.
|
||||
* strnlen_user: - Get the size of a string in user space.
|
||||
* @str: The string to measure.
|
||||
*
|
||||
* Context: User context only. This function may sleep.
|
||||
|
@ -1427,9 +1431,7 @@ static inline long __strnlen_user(const char __user *s, long n)
|
|||
*
|
||||
* Returns the size of the string INCLUDING the terminating NUL.
|
||||
* On exception, returns 0.
|
||||
*
|
||||
* If there is a limit on the length of a valid string, you may wish to
|
||||
* consider using strnlen_user() instead.
|
||||
* If the string is too long, returns a value greater than @n.
|
||||
*/
|
||||
static inline long strnlen_user(const char __user *s, long n)
|
||||
{
|
||||
|
|
|
@ -1045,7 +1045,7 @@
|
|||
#define __NR_seccomp (__NR_Linux + 316)
|
||||
#define __NR_getrandom (__NR_Linux + 317)
|
||||
#define __NR_memfd_create (__NR_Linux + 318)
|
||||
#define __NR_memfd_create (__NR_Linux + 319)
|
||||
#define __NR_bpf (__NR_Linux + 319)
|
||||
|
||||
/*
|
||||
* Offset of the last N32 flavoured syscall
|
||||
|
|
|
@ -208,7 +208,6 @@ bmips_reset_nmi_vec_end:
|
|||
END(bmips_reset_nmi_vec)
|
||||
|
||||
.set pop
|
||||
.previous
|
||||
|
||||
/***********************************************************************
|
||||
* CPU1 warm restart vector (used for second and subsequent boots).
|
||||
|
@ -281,5 +280,3 @@ LEAF(bmips_enable_xks01)
|
|||
jr ra
|
||||
|
||||
END(bmips_enable_xks01)
|
||||
|
||||
.previous
|
||||
|
|
|
@ -229,6 +229,7 @@ LEAF(mips_cps_core_init)
|
|||
nop
|
||||
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set mt
|
||||
|
||||
/* Only allow 1 TC per VPE to execute... */
|
||||
|
@ -345,6 +346,7 @@ LEAF(mips_cps_boot_vpes)
|
|||
nop
|
||||
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set mt
|
||||
|
||||
1: /* Enter VPE configuration state */
|
||||
|
|
|
@ -193,6 +193,32 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
|
|||
static char unknown_isa[] = KERN_ERR \
|
||||
"Unsupported ISA type, c0.config0: %d.";
|
||||
|
||||
static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
|
||||
{
|
||||
|
||||
unsigned int probability = c->tlbsize / c->tlbsizevtlb;
|
||||
|
||||
/*
|
||||
* 0 = All TLBWR instructions go to FTLB
|
||||
* 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
|
||||
* FTLB and 1 goes to the VTLB.
|
||||
* 2 = 7:1: As above with 7:1 ratio.
|
||||
* 3 = 3:1: As above with 3:1 ratio.
|
||||
*
|
||||
* Use the linear midpoint as the probability threshold.
|
||||
*/
|
||||
if (probability >= 12)
|
||||
return 1;
|
||||
else if (probability >= 6)
|
||||
return 2;
|
||||
else
|
||||
/*
|
||||
* So FTLB is less than 4 times bigger than VTLB.
|
||||
* A 3:1 ratio can still be useful though.
|
||||
*/
|
||||
return 3;
|
||||
}
|
||||
|
||||
static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
|
||||
{
|
||||
unsigned int config6;
|
||||
|
@ -203,9 +229,14 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
|
|||
case CPU_P5600:
|
||||
/* proAptiv & related cores use Config6 to enable the FTLB */
|
||||
config6 = read_c0_config6();
|
||||
/* Clear the old probability value */
|
||||
config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
|
||||
if (enable)
|
||||
/* Enable FTLB */
|
||||
write_c0_config6(config6 | MIPS_CONF6_FTLBEN);
|
||||
write_c0_config6(config6 |
|
||||
(calculate_ftlb_probability(c)
|
||||
<< MIPS_CONF6_FTLBP_SHIFT)
|
||||
| MIPS_CONF6_FTLBEN);
|
||||
else
|
||||
/* Disable FTLB */
|
||||
write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
|
||||
|
@ -757,31 +788,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->cputype = CPU_LOONGSON2;
|
||||
__cpu_name[cpu] = "ICT Loongson-2";
|
||||
set_elf_platform(cpu, "loongson2e");
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
break;
|
||||
case PRID_REV_LOONGSON2F:
|
||||
c->cputype = CPU_LOONGSON2;
|
||||
__cpu_name[cpu] = "ICT Loongson-2";
|
||||
set_elf_platform(cpu, "loongson2f");
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
break;
|
||||
case PRID_REV_LOONGSON3A:
|
||||
c->cputype = CPU_LOONGSON3;
|
||||
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
||||
__cpu_name[cpu] = "ICT Loongson-3";
|
||||
set_elf_platform(cpu, "loongson3a");
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
break;
|
||||
case PRID_REV_LOONGSON3B_R1:
|
||||
case PRID_REV_LOONGSON3B_R2:
|
||||
c->cputype = CPU_LOONGSON3;
|
||||
__cpu_name[cpu] = "ICT Loongson-3";
|
||||
set_elf_platform(cpu, "loongson3b");
|
||||
set_isa(c, MIPS_CPU_ISA_M64R1);
|
||||
break;
|
||||
}
|
||||
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS |
|
||||
MIPS_CPU_FPU | MIPS_CPU_LLSC |
|
||||
MIPS_CPU_32FPR;
|
||||
c->tlbsize = 64;
|
||||
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
|
||||
break;
|
||||
case PRID_IMP_LOONGSON_32: /* Loongson-1 */
|
||||
decode_configs(c);
|
||||
|
|
|
@ -18,31 +18,53 @@
|
|||
|
||||
#ifdef HAVE_JUMP_LABEL
|
||||
|
||||
#define J_RANGE_MASK ((1ul << 28) - 1)
|
||||
/*
|
||||
* Define parameters for the standard MIPS and the microMIPS jump
|
||||
* instruction encoding respectively:
|
||||
*
|
||||
* - the ISA bit of the target, either 0 or 1 respectively,
|
||||
*
|
||||
* - the amount the jump target address is shifted right to fit in the
|
||||
* immediate field of the machine instruction, either 2 or 1,
|
||||
*
|
||||
* - the mask determining the size of the jump region relative to the
|
||||
* delay-slot instruction, either 256MB or 128MB,
|
||||
*
|
||||
* - the jump target alignment, either 4 or 2 bytes.
|
||||
*/
|
||||
#define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS)
|
||||
#define J_RANGE_SHIFT (2 - J_ISA_BIT)
|
||||
#define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
|
||||
#define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
|
||||
|
||||
void arch_jump_label_transform(struct jump_entry *e,
|
||||
enum jump_label_type type)
|
||||
{
|
||||
union mips_instruction *insn_p;
|
||||
union mips_instruction insn;
|
||||
union mips_instruction *insn_p =
|
||||
(union mips_instruction *)(unsigned long)e->code;
|
||||
|
||||
/* Jump only works within a 256MB aligned region. */
|
||||
BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK));
|
||||
insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
|
||||
|
||||
/* Target must have 4 byte alignment. */
|
||||
BUG_ON((e->target & 3) != 0);
|
||||
/* Jump only works within an aligned region its delay slot is in. */
|
||||
BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
|
||||
|
||||
/* Target must have the right alignment and ISA must be preserved. */
|
||||
BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
|
||||
|
||||
if (type == JUMP_LABEL_ENABLE) {
|
||||
insn.j_format.opcode = j_op;
|
||||
insn.j_format.target = (e->target & J_RANGE_MASK) >> 2;
|
||||
insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
|
||||
insn.j_format.target = e->target >> J_RANGE_SHIFT;
|
||||
} else {
|
||||
insn.word = 0; /* nop */
|
||||
}
|
||||
|
||||
get_online_cpus();
|
||||
mutex_lock(&text_mutex);
|
||||
*insn_p = insn;
|
||||
if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
|
||||
insn_p->halfword[0] = insn.word >> 16;
|
||||
insn_p->halfword[1] = insn.word;
|
||||
} else
|
||||
*insn_p = insn;
|
||||
|
||||
flush_icache_range((unsigned long)insn_p,
|
||||
(unsigned long)insn_p + sizeof(*insn_p));
|
||||
|
|
|
@ -94,12 +94,12 @@ int rtlx_open(int index, int can_sleep)
|
|||
int ret = 0;
|
||||
|
||||
if (index >= RTLX_CHANNELS) {
|
||||
pr_debug(KERN_DEBUG "rtlx_open index out of range\n");
|
||||
pr_debug("rtlx_open index out of range\n");
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
if (atomic_inc_return(&channel_wqs[index].in_open) > 1) {
|
||||
pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index);
|
||||
pr_debug("rtlx_open channel %d already opened\n", index);
|
||||
ret = -EBUSY;
|
||||
goto out_fail;
|
||||
}
|
||||
|
|
|
@ -485,7 +485,7 @@ static void __init bootmem_init(void)
|
|||
* NOTE: historically plat_mem_setup did the entire platform initialization.
|
||||
* This was rather impractical because it meant plat_mem_setup had to
|
||||
* get away without any kind of memory allocator. To keep old code from
|
||||
* breaking plat_setup was just renamed to plat_setup and a second platform
|
||||
* breaking plat_setup was just renamed to plat_mem_setup and a second platform
|
||||
* initialization hook for anything else was introduced.
|
||||
*/
|
||||
|
||||
|
@ -493,7 +493,7 @@ static int usermem __initdata;
|
|||
|
||||
static int __init early_parse_mem(char *p)
|
||||
{
|
||||
unsigned long start, size;
|
||||
phys_t start, size;
|
||||
|
||||
/*
|
||||
* If a user specifies memory size, we
|
||||
|
|
|
@ -658,13 +658,13 @@ static int signal_setup(void)
|
|||
save_fp_context = _save_fp_context;
|
||||
restore_fp_context = _restore_fp_context;
|
||||
} else {
|
||||
save_fp_context = copy_fp_from_sigcontext;
|
||||
restore_fp_context = copy_fp_to_sigcontext;
|
||||
save_fp_context = copy_fp_to_sigcontext;
|
||||
restore_fp_context = copy_fp_from_sigcontext;
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
#else
|
||||
save_fp_context = copy_fp_from_sigcontext;;
|
||||
restore_fp_context = copy_fp_to_sigcontext;
|
||||
save_fp_context = copy_fp_to_sigcontext;
|
||||
restore_fp_context = copy_fp_from_sigcontext;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -503,6 +503,7 @@
|
|||
STOREB(t0, NBYTES-2(dst), .Ls_exc_p1\@)
|
||||
.Ldone\@:
|
||||
jr ra
|
||||
nop
|
||||
.if __memcpy == 1
|
||||
END(memcpy)
|
||||
.set __memcpy, 0
|
||||
|
|
|
@ -11,7 +11,8 @@ obj-$(CONFIG_PCI) += pci.o
|
|||
# Serial port support
|
||||
#
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
obj-$(CONFIG_SERIAL_8250) += serial.o
|
||||
loongson-serial-$(CONFIG_SERIAL_8250) := serial.o
|
||||
obj-y += $(loongson-serial-m) $(loongson-serial-y)
|
||||
obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
|
||||
obj-$(CONFIG_LOONGSON_MC146818) += rtc.o
|
||||
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
|
||||
static struct node_data prealloc__node_data[MAX_NUMNODES];
|
||||
unsigned char __node_distances[MAX_NUMNODES][MAX_NUMNODES];
|
||||
EXPORT_SYMBOL(__node_distances);
|
||||
struct node_data *__node_data[MAX_NUMNODES];
|
||||
EXPORT_SYMBOL(__node_data);
|
||||
|
||||
|
|
|
@ -299,6 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
|
||||
local_irq_save(flags);
|
||||
|
||||
htw_stop();
|
||||
pid = read_c0_entryhi() & ASID_MASK;
|
||||
address &= (PAGE_MASK << 1);
|
||||
write_c0_entryhi(address | pid);
|
||||
|
@ -346,6 +347,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
|
|||
tlb_write_indexed();
|
||||
}
|
||||
tlbw_use_hazard();
|
||||
htw_start();
|
||||
flush_itlb_vm(vma);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
@ -422,6 +424,7 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
|
||||
local_irq_save(flags);
|
||||
/* Save old context and create impossible VPN2 value */
|
||||
htw_stop();
|
||||
old_ctx = read_c0_entryhi();
|
||||
old_pagemask = read_c0_pagemask();
|
||||
wired = read_c0_wired();
|
||||
|
@ -443,6 +446,7 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||
|
||||
write_c0_entryhi(old_ctx);
|
||||
write_c0_pagemask(old_pagemask);
|
||||
htw_start();
|
||||
out:
|
||||
local_irq_restore(flags);
|
||||
return ret;
|
||||
|
|
|
@ -1872,8 +1872,16 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
|
|||
uasm_l_smp_pgtable_change(l, *p);
|
||||
#endif
|
||||
iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
|
||||
if (!m4kc_tlbp_war())
|
||||
if (!m4kc_tlbp_war()) {
|
||||
build_tlb_probe_entry(p);
|
||||
if (cpu_has_htw) {
|
||||
/* race condition happens, leaving */
|
||||
uasm_i_ehb(p);
|
||||
uasm_i_mfc0(p, wr.r3, C0_INDEX);
|
||||
uasm_il_bltz(p, r, wr.r3, label_leave);
|
||||
uasm_i_nop(p);
|
||||
}
|
||||
}
|
||||
return wr;
|
||||
}
|
||||
|
||||
|
|
|
@ -5,7 +5,7 @@
|
|||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
@ -76,8 +76,4 @@ static int __init led_init(void)
|
|||
return platform_device_register(&fled_device);
|
||||
}
|
||||
|
||||
module_init(led_init);
|
||||
|
||||
MODULE_AUTHOR("Chris Dearman <chris@mips.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("LED probe driver for SEAD-3");
|
||||
device_initcall(led_init);
|
||||
|
|
|
@ -1,6 +1,10 @@
|
|||
obj-y += setup.o nlm_hal.o cop2-ex.o dt.o
|
||||
obj-$(CONFIG_SMP) += wakeup.o
|
||||
obj-$(CONFIG_USB) += usb-init.o
|
||||
obj-$(CONFIG_USB) += usb-init-xlp2.o
|
||||
obj-$(CONFIG_SATA_AHCI) += ahci-init.o
|
||||
obj-$(CONFIG_SATA_AHCI) += ahci-init-xlp2.o
|
||||
ifdef CONFIG_USB
|
||||
obj-y += usb-init.o
|
||||
obj-y += usb-init-xlp2.o
|
||||
endif
|
||||
ifdef CONFIG_SATA_AHCI
|
||||
obj-y += ahci-init.o
|
||||
obj-y += ahci-init-xlp2.o
|
||||
endif
|
||||
|
|
|
@ -92,7 +92,7 @@ static inline int unwind_user_frame(struct stackframe *old_frame,
|
|||
/* This marks the end of the previous function,
|
||||
which means we overran. */
|
||||
break;
|
||||
stack_size = (unsigned) stack_adjustment;
|
||||
stack_size = (unsigned long) stack_adjustment;
|
||||
} else if (is_ra_save_ins(&ip)) {
|
||||
int ra_slot = ip.i_format.simmediate;
|
||||
if (ra_slot < 0)
|
||||
|
|
|
@ -107,6 +107,7 @@ static void router_recurse(klrou_t *router_a, klrou_t *router_b, int depth)
|
|||
}
|
||||
|
||||
unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
|
||||
EXPORT_SYMBOL(__node_distances);
|
||||
|
||||
static int __init compute_node_distance(nasid_t nasid_a, nasid_t nasid_b)
|
||||
{
|
||||
|
|
|
@ -159,8 +159,6 @@ struct pci_dn {
|
|||
|
||||
int pci_ext_config_space; /* for pci devices */
|
||||
|
||||
bool force_32bit_msi;
|
||||
|
||||
struct pci_dev *pcidev; /* back-pointer to the pci device */
|
||||
#ifdef CONFIG_EEH
|
||||
struct eeh_dev *edev; /* eeh device */
|
||||
|
|
|
@ -65,7 +65,7 @@ static ssize_t eeh_pe_state_show(struct device *dev,
|
|||
return -ENODEV;
|
||||
|
||||
state = eeh_ops->get_state(edev->pe, NULL);
|
||||
return sprintf(buf, "%0x08x %0x08x\n",
|
||||
return sprintf(buf, "0x%08x 0x%08x\n",
|
||||
state, edev->pe->state);
|
||||
}
|
||||
|
||||
|
|
|
@ -266,13 +266,3 @@ int pcibus_to_node(struct pci_bus *bus)
|
|||
}
|
||||
EXPORT_SYMBOL(pcibus_to_node);
|
||||
#endif
|
||||
|
||||
static void quirk_radeon_32bit_msi(struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dn *pdn = pci_get_pdn(dev);
|
||||
|
||||
if (pdn)
|
||||
pdn->force_32bit_msi = true;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi);
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi);
|
||||
|
|
|
@ -30,8 +30,8 @@
|
|||
V_FUNCTION_BEGIN(__kernel_getcpu)
|
||||
.cfi_startproc
|
||||
mfspr r5,SPRN_SPRG_VDSO_READ
|
||||
cmpdi cr0,r3,0
|
||||
cmpdi cr1,r4,0
|
||||
cmpwi cr0,r3,0
|
||||
cmpwi cr1,r4,0
|
||||
clrlwi r6,r5,16
|
||||
rlwinm r7,r5,16,31-15,31-0
|
||||
beq cr0,1f
|
||||
|
|
|
@ -57,7 +57,7 @@ static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
|
|||
};
|
||||
|
||||
/* Print things out */
|
||||
if (hmi_evt->version != OpalHMIEvt_V1) {
|
||||
if (hmi_evt->version < OpalHMIEvt_V1) {
|
||||
pr_err("HMI Interrupt, Unknown event version %d !\n",
|
||||
hmi_evt->version);
|
||||
return;
|
||||
|
|
|
@ -1509,7 +1509,6 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
|
|||
unsigned int is_64, struct msi_msg *msg)
|
||||
{
|
||||
struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
|
||||
struct pci_dn *pdn = pci_get_pdn(dev);
|
||||
unsigned int xive_num = hwirq - phb->msi_base;
|
||||
__be32 data;
|
||||
int rc;
|
||||
|
@ -1523,7 +1522,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
|
|||
return -ENXIO;
|
||||
|
||||
/* Force 32-bit MSI on some broken devices */
|
||||
if (pdn && pdn->force_32bit_msi)
|
||||
if (dev->no_64bit_msi)
|
||||
is_64 = 0;
|
||||
|
||||
/* Assign XIVE to PE */
|
||||
|
@ -1997,7 +1996,7 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
|
|||
if (is_kdump_kernel()) {
|
||||
pr_info(" Issue PHB reset ...\n");
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
|
||||
ioda_eeh_phb_reset(hose, OPAL_DEASSERT_RESET);
|
||||
ioda_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
|
||||
}
|
||||
|
||||
/* Configure M64 window */
|
||||
|
|
|
@ -50,7 +50,6 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
|||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
||||
struct pnv_phb *phb = hose->private_data;
|
||||
struct pci_dn *pdn = pci_get_pdn(pdev);
|
||||
struct msi_desc *entry;
|
||||
struct msi_msg msg;
|
||||
int hwirq;
|
||||
|
@ -60,7 +59,7 @@ static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
|
|||
if (WARN_ON(!phb) || !phb->msi_bmp.bitmap)
|
||||
return -ENODEV;
|
||||
|
||||
if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
|
||||
if (pdev->no_64bit_msi && !phb->msi32_support)
|
||||
return -ENODEV;
|
||||
|
||||
list_for_each_entry(entry, &pdev->msi_list, list) {
|
||||
|
|
|
@ -420,7 +420,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec_in, int type)
|
|||
*/
|
||||
again:
|
||||
if (type == PCI_CAP_ID_MSI) {
|
||||
if (pdn->force_32bit_msi) {
|
||||
if (pdev->no_64bit_msi) {
|
||||
rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
|
||||
if (rc < 0) {
|
||||
/*
|
||||
|
|
|
@ -361,7 +361,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
|
|||
cascade_data->virq = virt_msir;
|
||||
msi->cascade_array[irq_index] = cascade_data;
|
||||
|
||||
ret = request_irq(virt_msir, fsl_msi_cascade, 0,
|
||||
ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
|
||||
"fsl-msi-cascade", cascade_data);
|
||||
if (ret) {
|
||||
dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
|
||||
|
|
|
@ -293,10 +293,10 @@ static inline void disable_surveillance(void)
|
|||
args.token = rtas_token("set-indicator");
|
||||
if (args.token == RTAS_UNKNOWN_SERVICE)
|
||||
return;
|
||||
args.nargs = 3;
|
||||
args.nret = 1;
|
||||
args.nargs = cpu_to_be32(3);
|
||||
args.nret = cpu_to_be32(1);
|
||||
args.rets = &args.args[3];
|
||||
args.args[0] = SURVEILLANCE_TOKEN;
|
||||
args.args[0] = cpu_to_be32(SURVEILLANCE_TOKEN);
|
||||
args.args[1] = 0;
|
||||
args.args[2] = 0;
|
||||
enter_rtas(__pa(&args));
|
||||
|
|
|
@ -12,6 +12,14 @@ int dma_supported(struct device *dev, u64 mask);
|
|||
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
|
||||
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
|
||||
|
||||
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
/* Since dma_{alloc,free}_noncoherent() allocated coherent memory, this
|
||||
* routine can be a nop.
|
||||
*/
|
||||
}
|
||||
|
||||
extern struct dma_map_ops *dma_ops;
|
||||
extern struct dma_map_ops *leon_dma_ops;
|
||||
extern struct dma_map_ops pci32_dma_ops;
|
||||
|
|
|
@ -144,7 +144,7 @@ config INSTRUCTION_DECODER
|
|||
|
||||
config PERF_EVENTS_INTEL_UNCORE
|
||||
def_bool y
|
||||
depends on PERF_EVENTS && SUP_SUP_INTEL && PCI
|
||||
depends on PERF_EVENTS && CPU_SUP_INTEL && PCI
|
||||
|
||||
config OUTPUT_FORMAT
|
||||
string
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
#define THREAD_SIZE_ORDER 1
|
||||
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 0
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 0
|
||||
#define DEBUG_STACK 0
|
||||
|
|
|
@ -14,12 +14,11 @@
|
|||
#define IRQ_STACK_ORDER 2
|
||||
#define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER)
|
||||
|
||||
#define STACKFAULT_STACK 1
|
||||
#define DOUBLEFAULT_STACK 2
|
||||
#define NMI_STACK 3
|
||||
#define DEBUG_STACK 4
|
||||
#define MCE_STACK 5
|
||||
#define N_EXCEPTION_STACKS 5 /* hw limit: 7 */
|
||||
#define DOUBLEFAULT_STACK 1
|
||||
#define NMI_STACK 2
|
||||
#define DEBUG_STACK 3
|
||||
#define MCE_STACK 4
|
||||
#define N_EXCEPTION_STACKS 4 /* hw limit: 7 */
|
||||
|
||||
#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT)
|
||||
#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1))
|
||||
|
|
|
@ -141,7 +141,7 @@ struct thread_info {
|
|||
/* Only used for 64 bit */
|
||||
#define _TIF_DO_NOTIFY_MASK \
|
||||
(_TIF_SIGPENDING | _TIF_MCE_NOTIFY | _TIF_NOTIFY_RESUME | \
|
||||
_TIF_USER_RETURN_NOTIFY)
|
||||
_TIF_USER_RETURN_NOTIFY | _TIF_UPROBE)
|
||||
|
||||
/* flags to check in __switch_to() */
|
||||
#define _TIF_WORK_CTXSW \
|
||||
|
|
|
@ -39,6 +39,7 @@ asmlinkage void simd_coprocessor_error(void);
|
|||
|
||||
#ifdef CONFIG_TRACING
|
||||
asmlinkage void trace_page_fault(void);
|
||||
#define trace_stack_segment stack_segment
|
||||
#define trace_divide_error divide_error
|
||||
#define trace_bounds bounds
|
||||
#define trace_invalid_op invalid_op
|
||||
|
|
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Reference in New Issue