mirror of https://gitee.com/openkylin/linux.git
Merge branch 'pci/aspm'
- Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) * pci/aspm: PCI/ASPM: Save LTR Capability for suspend/resume PCI/ASPM: Use LTR if already enabled by platform
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commit
2fcc19b341
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@ -1233,7 +1233,6 @@ static void pci_restore_pcie_state(struct pci_dev *dev)
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pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
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}
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static int pci_save_pcix_state(struct pci_dev *dev)
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{
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int pos;
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@ -1270,6 +1269,45 @@ static void pci_restore_pcix_state(struct pci_dev *dev)
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pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
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}
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static void pci_save_ltr_state(struct pci_dev *dev)
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{
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int ltr;
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struct pci_cap_saved_state *save_state;
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u16 *cap;
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if (!pci_is_pcie(dev))
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return;
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ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
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if (!ltr)
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return;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
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if (!save_state) {
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pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
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return;
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}
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cap = (u16 *)&save_state->cap.data[0];
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pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
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pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
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}
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static void pci_restore_ltr_state(struct pci_dev *dev)
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{
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struct pci_cap_saved_state *save_state;
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int ltr;
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u16 *cap;
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save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
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ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
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if (!save_state || !ltr)
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return;
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cap = (u16 *)&save_state->cap.data[0];
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pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
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pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
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}
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/**
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* pci_save_state - save the PCI configuration space of a device before suspending
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@ -1291,6 +1329,7 @@ int pci_save_state(struct pci_dev *dev)
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if (i != 0)
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return i;
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pci_save_ltr_state(dev);
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pci_save_dpc_state(dev);
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return pci_save_vc_state(dev);
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}
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@ -1390,7 +1429,12 @@ void pci_restore_state(struct pci_dev *dev)
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if (!dev->state_saved)
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return;
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/* PCI Express register must be restored first */
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/*
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* Restore max latencies (in the LTR capability) before enabling
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* LTR itself (in the PCIe capability).
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*/
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pci_restore_ltr_state(dev);
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pci_restore_pcie_state(dev);
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pci_restore_pasid_state(dev);
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pci_restore_pri_state(dev);
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@ -2998,6 +3042,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
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if (error)
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pci_err(dev, "unable to preallocate PCI-X save buffer\n");
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error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
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2 * sizeof(u16));
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if (error)
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pci_err(dev, "unable to allocate suspend buffer for LTR\n");
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pci_allocate_vc_save_buffers(dev);
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}
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@ -2069,11 +2069,8 @@ static void pci_configure_ltr(struct pci_dev *dev)
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{
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#ifdef CONFIG_PCIEASPM
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struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
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u32 cap;
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struct pci_dev *bridge;
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if (!host->native_ltr)
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return;
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u32 cap, ctl;
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if (!pci_is_pcie(dev))
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return;
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@ -2082,22 +2079,35 @@ static void pci_configure_ltr(struct pci_dev *dev)
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if (!(cap & PCI_EXP_DEVCAP2_LTR))
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return;
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/*
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* Software must not enable LTR in an Endpoint unless the Root
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* Complex and all intermediate Switches indicate support for LTR.
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* PCIe r3.1, sec 6.18.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
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dev->ltr_path = 1;
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else {
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pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
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if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
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dev->ltr_path = 1;
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return;
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}
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bridge = pci_upstream_bridge(dev);
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if (bridge && bridge->ltr_path)
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dev->ltr_path = 1;
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return;
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}
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if (dev->ltr_path)
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if (!host->native_ltr)
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return;
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/*
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* Software must not enable LTR in an Endpoint unless the Root
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* Complex and all intermediate Switches indicate support for LTR.
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* PCIe r4.0, sec 6.18.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
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((bridge = pci_upstream_bridge(dev)) &&
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bridge->ltr_path)) {
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
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PCI_EXP_DEVCTL2_LTR_EN);
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dev->ltr_path = 1;
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}
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#endif
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}
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