mirror of https://gitee.com/openkylin/linux.git
scsi: lpfc: Change default queue allocation for reduced memory consumption
By default, the driver attempts to allocate a hdwq per logical cpu in order to provide good cpu affinity. Some systems have extremely high cpu counts and this can significantly raise memory consumption. In testing on x86 platforms (non-AMD) it is found that sharing of a hdwq by a physical cpu and its HT cpu can occur with little performance degredation. By sharing, the hdwq count can be halved, significantly reducing the memory overhead. Change the default behavior of the driver on non-AMD x86 platforms to share a hdwq by the cpu and its HT cpu. Link: https://lore.kernel.org/r/20200501214310.91713-6-jsmart2021@gmail.com Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Dick Kennedy <dick.kennedy@broadcom.com> Signed-off-by: James Smart <jsmart2021@gmail.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Dick Kennedy
Martin K. Petersen
parent
f809da6db6
commit
3048e3e805
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@ -627,6 +627,19 @@ struct lpfc_ras_fwlog {
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enum ras_state state; /* RAS logging running state */
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};
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enum lpfc_irq_chann_mode {
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/* Assign IRQs to all possible cpus that have hardware queues */
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NORMAL_MODE,
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/* Assign IRQs only to cpus on the same numa node as HBA */
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NUMA_MODE,
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/* Assign IRQs only on non-hyperthreaded CPUs. This is the
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* same as normal_mode, but assign IRQS only on physical CPUs.
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*/
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NHT_MODE,
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};
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struct lpfc_hba {
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/* SCSI interface function jump table entries */
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struct lpfc_io_buf * (*lpfc_get_scsi_buf)
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@ -835,7 +848,6 @@ struct lpfc_hba {
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uint32_t cfg_fcp_mq_threshold;
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uint32_t cfg_hdw_queue;
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uint32_t cfg_irq_chann;
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uint32_t cfg_irq_numa;
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uint32_t cfg_suppress_rsp;
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uint32_t cfg_nvme_oas;
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uint32_t cfg_nvme_embed_cmd;
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@ -1003,6 +1015,7 @@ struct lpfc_hba {
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mempool_t *active_rrq_pool;
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struct fc_host_statistics link_stats;
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enum lpfc_irq_chann_mode irq_chann_mode;
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enum intr_type_t intr_type;
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uint32_t intr_mode;
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#define LPFC_INTR_ERROR 0xFFFFFFFF
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@ -1314,19 +1327,19 @@ lpfc_phba_elsring(struct lpfc_hba *phba)
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}
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/**
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* lpfc_next_online_numa_cpu - Finds next online CPU on NUMA node
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* @numa_mask: Pointer to phba's numa_mask member.
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* lpfc_next_online_cpu - Finds next online CPU on cpumask
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* @mask: Pointer to phba's cpumask member.
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* @start: starting cpu index
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*
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* Note: If no valid cpu found, then nr_cpu_ids is returned.
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*
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**/
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static inline unsigned int
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lpfc_next_online_numa_cpu(const struct cpumask *numa_mask, unsigned int start)
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lpfc_next_online_cpu(const struct cpumask *mask, unsigned int start)
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{
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unsigned int cpu_it;
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for_each_cpu_wrap(cpu_it, numa_mask, start) {
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for_each_cpu_wrap(cpu_it, mask, start) {
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if (cpu_online(cpu_it))
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break;
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}
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@ -5704,17 +5704,69 @@ LPFC_ATTR_R(hdw_queue,
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LPFC_HBA_HDWQ_MIN, LPFC_HBA_HDWQ_MAX,
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"Set the number of I/O Hardware Queues");
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static inline void
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lpfc_assign_default_irq_numa(struct lpfc_hba *phba)
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#if IS_ENABLED(CONFIG_X86)
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/**
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* lpfc_cpumask_irq_mode_init - initalizes cpumask of phba based on
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* irq_chann_mode
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* @phba: Pointer to HBA context object.
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**/
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static void
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lpfc_cpumask_irq_mode_init(struct lpfc_hba *phba)
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{
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unsigned int cpu, first_cpu, numa_node = NUMA_NO_NODE;
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const struct cpumask *sibling_mask;
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struct cpumask *aff_mask = &phba->sli4_hba.irq_aff_mask;
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cpumask_clear(aff_mask);
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if (phba->irq_chann_mode == NUMA_MODE) {
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/* Check if we're a NUMA architecture */
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numa_node = dev_to_node(&phba->pcidev->dev);
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if (numa_node == NUMA_NO_NODE) {
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phba->irq_chann_mode = NORMAL_MODE;
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return;
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}
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}
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for_each_possible_cpu(cpu) {
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switch (phba->irq_chann_mode) {
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case NUMA_MODE:
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if (cpu_to_node(cpu) == numa_node)
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cpumask_set_cpu(cpu, aff_mask);
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break;
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case NHT_MODE:
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sibling_mask = topology_sibling_cpumask(cpu);
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first_cpu = cpumask_first(sibling_mask);
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if (first_cpu < nr_cpu_ids)
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cpumask_set_cpu(first_cpu, aff_mask);
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break;
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default:
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break;
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}
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}
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}
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#endif
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static void
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lpfc_assign_default_irq_chann(struct lpfc_hba *phba)
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{
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#if IS_ENABLED(CONFIG_X86)
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/* If AMD architecture, then default is LPFC_IRQ_CHANN_NUMA */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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phba->cfg_irq_numa = 1;
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else
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phba->cfg_irq_numa = 0;
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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/* If AMD architecture, then default is NUMA_MODE */
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phba->irq_chann_mode = NUMA_MODE;
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break;
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case X86_VENDOR_INTEL:
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/* If Intel architecture, then default is no hyperthread mode */
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phba->irq_chann_mode = NHT_MODE;
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break;
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default:
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phba->irq_chann_mode = NORMAL_MODE;
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break;
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}
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lpfc_cpumask_irq_mode_init(phba);
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#else
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phba->cfg_irq_numa = 0;
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phba->irq_chann_mode = NORMAL_MODE;
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#endif
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}
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@ -5726,6 +5778,7 @@ lpfc_assign_default_irq_numa(struct lpfc_hba *phba)
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*
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* 0 = Configure number of IRQ Channels to:
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* if AMD architecture, number of CPUs on HBA's NUMA node
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* if Intel architecture, number of physical CPUs.
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* otherwise, number of active CPUs.
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* [1,256] = Manually specify how many IRQ Channels to use.
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*
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@ -5751,35 +5804,44 @@ MODULE_PARM_DESC(lpfc_irq_chann, "Set number of interrupt vectors to allocate");
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static int
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lpfc_irq_chann_init(struct lpfc_hba *phba, uint32_t val)
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{
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const struct cpumask *numa_mask;
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const struct cpumask *aff_mask;
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if (phba->cfg_use_msi != 2) {
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lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
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"8532 use_msi = %u ignoring cfg_irq_numa\n",
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phba->cfg_use_msi);
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phba->cfg_irq_numa = 0;
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_MIN;
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phba->irq_chann_mode = NORMAL_MODE;
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_DEF;
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return 0;
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}
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/* Check if default setting was passed */
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if (val == LPFC_IRQ_CHANN_DEF)
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lpfc_assign_default_irq_numa(phba);
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lpfc_assign_default_irq_chann(phba);
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if (phba->cfg_irq_numa) {
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numa_mask = &phba->sli4_hba.numa_mask;
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if (phba->irq_chann_mode != NORMAL_MODE) {
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aff_mask = &phba->sli4_hba.irq_aff_mask;
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if (cpumask_empty(numa_mask)) {
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if (cpumask_empty(aff_mask)) {
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lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
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"8533 Could not identify NUMA node, "
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"ignoring cfg_irq_numa\n");
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phba->cfg_irq_numa = 0;
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_MIN;
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"8533 Could not identify CPUS for "
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"mode %d, ignoring\n",
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phba->irq_chann_mode);
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phba->irq_chann_mode = NORMAL_MODE;
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_DEF;
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} else {
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phba->cfg_irq_chann = cpumask_weight(numa_mask);
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phba->cfg_irq_chann = cpumask_weight(aff_mask);
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/* If no hyperthread mode, then set hdwq count to
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* aff_mask weight as well
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*/
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if (phba->irq_chann_mode == NHT_MODE)
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phba->cfg_hdw_queue = phba->cfg_irq_chann;
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lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
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"8543 lpfc_irq_chann set to %u "
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"(numa)\n", phba->cfg_irq_chann);
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"(mode: %d)\n", phba->cfg_irq_chann,
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phba->irq_chann_mode);
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}
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} else {
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if (val > LPFC_IRQ_CHANN_MAX) {
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@ -5790,7 +5852,7 @@ lpfc_irq_chann_init(struct lpfc_hba *phba, uint32_t val)
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val,
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LPFC_IRQ_CHANN_MIN,
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LPFC_IRQ_CHANN_MAX);
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_MIN;
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phba->cfg_irq_chann = LPFC_IRQ_CHANN_DEF;
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return -EINVAL;
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}
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phba->cfg_irq_chann = val;
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@ -6022,29 +6022,6 @@ static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
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return;
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}
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/**
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* lpfc_cpumask_of_node_init - initalizes cpumask of phba's NUMA node
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* @phba: Pointer to HBA context object.
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*
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**/
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static void
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lpfc_cpumask_of_node_init(struct lpfc_hba *phba)
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{
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unsigned int cpu, numa_node;
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struct cpumask *numa_mask = &phba->sli4_hba.numa_mask;
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cpumask_clear(numa_mask);
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/* Check if we're a NUMA architecture */
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numa_node = dev_to_node(&phba->pcidev->dev);
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if (numa_node == NUMA_NO_NODE)
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return;
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for_each_possible_cpu(cpu)
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if (cpu_to_node(cpu) == numa_node)
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cpumask_set_cpu(cpu, numa_mask);
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}
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/**
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* lpfc_enable_pci_dev - Enable a generic PCI device.
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* @phba: pointer to lpfc hba data structure.
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@ -6483,7 +6460,6 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
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phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
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phba->sli4_hba.num_possible_cpu = cpumask_last(cpu_possible_mask) + 1;
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phba->sli4_hba.curr_disp_cpu = 0;
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lpfc_cpumask_of_node_init(phba);
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/* Get all the module params for configuring this host */
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lpfc_get_cfgparam(phba);
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@ -6691,6 +6667,13 @@ lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
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#endif
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/* Not supported for NVMET */
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phba->cfg_xri_rebalancing = 0;
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if (phba->irq_chann_mode == NHT_MODE) {
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phba->cfg_irq_chann =
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phba->sli4_hba.num_present_cpu;
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phba->cfg_hdw_queue =
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phba->sli4_hba.num_present_cpu;
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phba->irq_chann_mode = NORMAL_MODE;
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}
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break;
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}
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}
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@ -7032,7 +7015,7 @@ lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
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phba->sli4_hba.num_possible_cpu = 0;
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phba->sli4_hba.num_present_cpu = 0;
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phba->sli4_hba.curr_disp_cpu = 0;
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cpumask_clear(&phba->sli4_hba.numa_mask);
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cpumask_clear(&phba->sli4_hba.irq_aff_mask);
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/* Free memory allocated for fast-path work queue handles */
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kfree(phba->sli4_hba.hba_eq_hdl);
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@ -11287,11 +11270,12 @@ lpfc_irq_clear_aff(struct lpfc_hba_eq_hdl *eqhdl)
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* @offline: true, cpu is going offline. false, cpu is coming online.
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*
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* If cpu is going offline, we'll try our best effort to find the next
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* online cpu on the phba's NUMA node and migrate all offlining IRQ affinities.
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* online cpu on the phba's original_mask and migrate all offlining IRQ
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* affinities.
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*
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* If cpu is coming online, reaffinitize the IRQ back to the onlineng cpu.
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* If cpu is coming online, reaffinitize the IRQ back to the onlining cpu.
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*
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* Note: Call only if cfg_irq_numa is enabled, otherwise rely on
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* Note: Call only if NUMA or NHT mode is enabled, otherwise rely on
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* PCI_IRQ_AFFINITY to auto-manage IRQ affinity.
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*
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**/
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@ -11301,14 +11285,14 @@ lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
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struct lpfc_vector_map_info *cpup;
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struct cpumask *aff_mask;
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unsigned int cpu_select, cpu_next, idx;
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const struct cpumask *numa_mask;
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const struct cpumask *orig_mask;
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if (!phba->cfg_irq_numa)
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if (phba->irq_chann_mode == NORMAL_MODE)
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return;
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numa_mask = &phba->sli4_hba.numa_mask;
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orig_mask = &phba->sli4_hba.irq_aff_mask;
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if (!cpumask_test_cpu(cpu, numa_mask))
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if (!cpumask_test_cpu(cpu, orig_mask))
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return;
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cpup = &phba->sli4_hba.cpu_map[cpu];
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@ -11317,9 +11301,9 @@ lpfc_irq_rebalance(struct lpfc_hba *phba, unsigned int cpu, bool offline)
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return;
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if (offline) {
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/* Find next online CPU on NUMA node */
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cpu_next = cpumask_next_wrap(cpu, numa_mask, cpu, true);
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cpu_select = lpfc_next_online_numa_cpu(numa_mask, cpu_next);
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/* Find next online CPU on original mask */
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cpu_next = cpumask_next_wrap(cpu, orig_mask, cpu, true);
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cpu_select = lpfc_next_online_cpu(orig_mask, cpu_next);
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/* Found a valid CPU */
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if ((cpu_select < nr_cpu_ids) && (cpu_select != cpu)) {
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@ -11434,7 +11418,7 @@ lpfc_sli4_enable_msix(struct lpfc_hba *phba)
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{
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int vectors, rc, index;
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char *name;
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const struct cpumask *numa_mask = NULL;
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const struct cpumask *aff_mask = NULL;
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unsigned int cpu = 0, cpu_cnt = 0, cpu_select = nr_cpu_ids;
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struct lpfc_hba_eq_hdl *eqhdl;
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const struct cpumask *maskp;
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@ -11444,16 +11428,18 @@ lpfc_sli4_enable_msix(struct lpfc_hba *phba)
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/* Set up MSI-X multi-message vectors */
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vectors = phba->cfg_irq_chann;
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if (phba->cfg_irq_numa) {
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numa_mask = &phba->sli4_hba.numa_mask;
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cpu_cnt = cpumask_weight(numa_mask);
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if (phba->irq_chann_mode != NORMAL_MODE)
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aff_mask = &phba->sli4_hba.irq_aff_mask;
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if (aff_mask) {
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cpu_cnt = cpumask_weight(aff_mask);
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vectors = min(phba->cfg_irq_chann, cpu_cnt);
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/* cpu: iterates over numa_mask including offline or online
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* cpu_select: iterates over online numa_mask to set affinity
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/* cpu: iterates over aff_mask including offline or online
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* cpu_select: iterates over online aff_mask to set affinity
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*/
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cpu = cpumask_first(numa_mask);
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cpu_select = lpfc_next_online_numa_cpu(numa_mask, cpu);
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cpu = cpumask_first(aff_mask);
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cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
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} else {
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flags |= PCI_IRQ_AFFINITY;
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}
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@ -11487,7 +11473,7 @@ lpfc_sli4_enable_msix(struct lpfc_hba *phba)
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eqhdl->irq = pci_irq_vector(phba->pcidev, index);
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if (phba->cfg_irq_numa) {
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if (aff_mask) {
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/* If found a neighboring online cpu, set affinity */
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if (cpu_select < nr_cpu_ids)
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lpfc_irq_set_aff(eqhdl, cpu_select);
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@ -11497,11 +11483,11 @@ lpfc_sli4_enable_msix(struct lpfc_hba *phba)
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LPFC_CPU_FIRST_IRQ,
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cpu);
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/* Iterate to next offline or online cpu in numa_mask */
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cpu = cpumask_next(cpu, numa_mask);
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/* Iterate to next offline or online cpu in aff_mask */
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cpu = cpumask_next(cpu, aff_mask);
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/* Find next online cpu in numa_mask to set affinity */
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cpu_select = lpfc_next_online_numa_cpu(numa_mask, cpu);
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/* Find next online cpu in aff_mask to set affinity */
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cpu_select = lpfc_next_online_cpu(aff_mask, cpu);
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} else if (vectors == 1) {
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||||
cpu = cpumask_first(cpu_present_mask);
|
||||
lpfc_assign_eq_map_info(phba, index, LPFC_CPU_FIRST_IRQ,
|
||||
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|
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|||
|
|
@ -920,7 +920,7 @@ struct lpfc_sli4_hba {
|
|||
struct lpfc_vector_map_info *cpu_map;
|
||||
uint16_t num_possible_cpu;
|
||||
uint16_t num_present_cpu;
|
||||
struct cpumask numa_mask;
|
||||
struct cpumask irq_aff_mask;
|
||||
uint16_t curr_disp_cpu;
|
||||
struct lpfc_eq_intr_info __percpu *eq_info;
|
||||
#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
|
||||
|
|
|
|||
Loading…
Reference in New Issue