mirror of https://gitee.com/openkylin/linux.git
perf parse-events: Create two hybrid cache events
For cache events, they have pre-defined configs. The kernel needs
to know where the cache event comes from (e.g. from cpu_core pmu
or from cpu_atom pmu). But the perf type PERF_TYPE_HW_CACHE
can't carry pmu information.
Now the type PERF_TYPE_HW_CACHE is extended to be PMU aware type.
The PMU type ID is stored at attr.config[63:32].
When enabling a hybrid cache event without specified pmu, such as,
'perf stat -e LLC-loads -a', two events are created
automatically. One is for atom, the other is for core.
# perf stat -e LLC-loads -a -vv -- sleep 1
Control descriptor is not initialized
------------------------------------------------------------
perf_event_attr:
type 3
size 120
config 0x400000002
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8 = 3
------------------------------------------------------------
...
------------------------------------------------------------
perf_event_attr:
type 3
size 120
config 0x400000002
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 15 group_fd -1 flags 0x8 = 19
------------------------------------------------------------
perf_event_attr:
type 3
size 120
config 0x800000002
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 16 group_fd -1 flags 0x8 = 20
------------------------------------------------------------
...
------------------------------------------------------------
perf_event_attr:
type 3
size 120
config 0x800000002
sample_type IDENTIFIER
read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING
disabled 1
inherit 1
exclude_guest 1
------------------------------------------------------------
sys_perf_event_open: pid -1 cpu 23 group_fd -1 flags 0x8 = 27
LLC-loads: 0: 1507 1001800280 1001800280
LLC-loads: 1: 666 1001812250 1001812250
LLC-loads: 2: 3353 1001813453 1001813453
LLC-loads: 3: 514 1001848795 1001848795
LLC-loads: 4: 627 1001952832 1001952832
LLC-loads: 5: 4399 1001451154 1001451154
LLC-loads: 6: 1240 1001481052 1001481052
LLC-loads: 7: 478 1001520348 1001520348
LLC-loads: 8: 691 1001551236 1001551236
LLC-loads: 9: 310 1001578945 1001578945
LLC-loads: 10: 1018 1001594354 1001594354
LLC-loads: 11: 3656 1001622355 1001622355
LLC-loads: 12: 882 1001661416 1001661416
LLC-loads: 13: 506 1001693963 1001693963
LLC-loads: 14: 3547 1001721013 1001721013
LLC-loads: 15: 1399 1001734818 1001734818
LLC-loads: 0: 1314 1001793826 1001793826
LLC-loads: 1: 2857 1001752764 1001752764
LLC-loads: 2: 646 1001830694 1001830694
LLC-loads: 3: 1612 1001864861 1001864861
LLC-loads: 4: 2244 1001912381 1001912381
LLC-loads: 5: 1255 1001943889 1001943889
LLC-loads: 6: 4624 1002021109 1002021109
LLC-loads: 7: 2703 1001959302 1001959302
LLC-loads: 24793 16026838264 16026838264
LLC-loads: 17255 8015078826 8015078826
Performance counter stats for 'system wide':
24,793 cpu_core/LLC-loads/
17,255 cpu_atom/LLC-loads/
1.001970988 seconds time elapsed
0x4 in 0x400000002 indicates the cpu_core pmu.
0x8 in 0x800000002 indicates the cpu_atom pmu.
Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
Reviewed-by: Jiri Olsa <jolsa@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210427070139.25256-10-yao.jin@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Jin Yao
Arnaldo Carvalho de Melo
parent
9cbfa2f64c
commit
30def61f64
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@ -98,3 +98,26 @@ int parse_events__add_numeric_hybrid(struct parse_events_state *parse_state,
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return -1;
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}
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int parse_events__add_cache_hybrid(struct list_head *list, int *idx,
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struct perf_event_attr *attr, char *name,
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struct list_head *config_terms,
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bool *hybrid)
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{
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struct perf_pmu *pmu;
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int ret;
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*hybrid = false;
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if (!perf_pmu__has_hybrid())
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return 0;
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*hybrid = true;
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perf_pmu__for_each_hybrid_pmu(pmu) {
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ret = create_event_hybrid(PERF_TYPE_HW_CACHE, idx, list,
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attr, name, config_terms, pmu);
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if (ret)
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return ret;
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}
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return 0;
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}
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@ -14,4 +14,9 @@ int parse_events__add_numeric_hybrid(struct parse_events_state *parse_state,
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char *name, struct list_head *config_terms,
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bool *hybrid);
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int parse_events__add_cache_hybrid(struct list_head *list, int *idx,
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struct perf_event_attr *attr, char *name,
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struct list_head *config_terms,
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bool *hybrid);
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#endif /* __PERF_PARSE_EVENTS_HYBRID_H */
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@ -460,7 +460,8 @@ int parse_events_add_cache(struct list_head *list, int *idx,
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char name[MAX_NAME_LEN], *config_name;
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int cache_type = -1, cache_op = -1, cache_result = -1;
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char *op_result[2] = { op_result1, op_result2 };
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int i, n;
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int i, n, ret;
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bool hybrid;
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/*
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* No fallback - if we cannot get a clear cache type
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@ -520,6 +521,13 @@ int parse_events_add_cache(struct list_head *list, int *idx,
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if (get_config_terms(head_config, &config_terms))
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return -ENOMEM;
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}
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ret = parse_events__add_cache_hybrid(list, idx, &attr,
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config_name ? : name, &config_terms,
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&hybrid);
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if (hybrid)
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return ret;
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return add_event(list, idx, &attr, config_name ? : name, &config_terms);
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}
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