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drm: sti: add bindings for DRM driver
Add DRM/KMS driver bindings documentation. Describe the required properties for each of the hardware IPs drivers. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
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Benjamin Gaignard
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STMicroelectronics stih4xx platforms
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- sti-vtg: video timing generator
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Required properties:
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- compatible: "st,vtg"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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Optional properties:
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- interrupts : VTG interrupt number to the CPU.
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- st,slave: phandle on a slave vtg
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- sti-vtac: video timing advanced inter dye communication Rx and TX
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Required properties:
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- compatible: "st,vtac-main" or "st,vtac-aux"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- clocks: from common clock binding: handle hardware IP needed clocks, the
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number of clocks may depend of the SoC type.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: names of the clocks listed in clocks property in the same
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order.
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- sti-display-subsystem: Master device for DRM sub-components
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This device must be the parent of all the sub-components and is responsible
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of bind them.
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Required properties:
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- compatible: "st,sti-display-subsystem"
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- ranges: to allow probing of subdevices
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- sti-compositor: frame compositor engine
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must be a child of sti-display-subsystem
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Required properties:
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- compatible: "st,stih<chip>-compositor"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- clocks: from common clock binding: handle hardware IP needed clocks, the
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number of clocks may depend of the SoC type.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: names of the clocks listed in clocks property in the same
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order.
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- resets: resets to be used by the device
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See ../reset/reset.txt for details.
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- reset-names: names of the resets listed in resets property in the same
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order.
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- st,vtg: phandle(s) on vtg device (main and aux) nodes.
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- sti-tvout: video out hardware block
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must be a child of sti-display-subsystem
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Required properties:
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- compatible: "st,stih<chip>-tvout"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- reg-names: names of the mapped memory regions listed in regs property in
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the same order.
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- resets: resets to be used by the device
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See ../reset/reset.txt for details.
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- reset-names: names of the resets listed in resets property in the same
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order.
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- ranges: to allow probing of subdevices
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- sti-hdmi: hdmi output block
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must be a child of sti-tvout
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Required properties:
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- compatible: "st,stih<chip>-hdmi";
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- reg-names: names of the mapped memory regions listed in regs property in
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the same order.
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- interrupts : HDMI interrupt number to the CPU.
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- interrupt-names: name of the interrupts listed in interrupts property in
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the same order
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- clocks: from common clock binding: handle hardware IP needed clocks, the
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number of clocks may depend of the SoC type.
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- clock-names: names of the clocks listed in clocks property in the same
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order.
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- hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
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sti-hda:
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Required properties:
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must be a child of sti-tvout
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- compatible: "st,stih<chip>-hda"
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- reg: Physical base address of the IP registers and length of memory mapped region.
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- reg-names: names of the mapped memory regions listed in regs property in
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the same order.
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- clocks: from common clock binding: handle hardware IP needed clocks, the
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number of clocks may depend of the SoC type.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: names of the clocks listed in clocks property in the same
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order.
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Example:
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/ {
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...
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vtg_main_slave: sti-vtg-main-slave@fe85A800 {
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compatible = "st,vtg";
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reg = <0xfe85A800 0x300>;
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interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>;
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};
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vtg_main: sti-vtg-main-master@fd348000 {
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compatible = "st,vtg";
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reg = <0xfd348000 0x400>;
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st,slave = <&vtg_main_slave>;
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};
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vtg_aux_slave: sti-vtg-aux-slave@fd348400 {
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compatible = "st,vtg";
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reg = <0xfe858200 0x300>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>;
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};
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vtg_aux: sti-vtg-aux-master@fd348400 {
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compatible = "st,vtg";
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reg = <0xfd348400 0x400>;
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st,slave = <&vtg_aux_slave>;
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};
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sti-vtac-rx-main@fee82800 {
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compatible = "st,vtac-main";
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reg = <0xfee82800 0x200>;
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clock-names = "vtac";
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clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>;
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};
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sti-vtac-rx-aux@fee82a00 {
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compatible = "st,vtac-aux";
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reg = <0xfee82a00 0x200>;
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clock-names = "vtac";
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clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>;
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};
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sti-vtac-tx-main@fd349000 {
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compatible = "st,vtac-main";
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reg = <0xfd349000 0x200>, <0xfd320000 0x10000>;
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clock-names = "vtac";
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clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
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};
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sti-vtac-tx-aux@fd349200 {
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compatible = "st,vtac-aux";
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reg = <0xfd349200 0x200>, <0xfd320000 0x10000>;
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clock-names = "vtac";
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clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>;
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};
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sti-display-subsystem {
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compatible = "st,sti-display-subsystem";
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ranges;
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sti-compositor@fd340000 {
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compatible = "st,stih416-compositor";
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reg = <0xfd340000 0x1000>;
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clock-names = "compo_main", "compo_aux",
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"pix_main", "pix_aux";
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clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>,
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<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>;
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reset-names = "compo-main", "compo-aux";
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resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
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st,vtg = <&vtg_main>, <&vtg_aux>;
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};
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sti-tvout@fe000000 {
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compatible = "st,stih416-tvout";
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reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
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reg-names = "tvout-reg", "hda-reg", "syscfg";
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reset-names = "tvout";
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resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
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ranges;
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sti-hdmi@fe85c000 {
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compatible = "st,stih416-hdmi";
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reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
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reg-names = "hdmi-reg", "syscfg";
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interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
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interrupt-names = "irq";
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clock-names = "pix", "tmds", "phy", "audio";
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clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
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hdmi,hpd-gpio = <&PIO2 5>;
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};
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sti-hda@fe85a000 {
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compatible = "st,stih416-hda";
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reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
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reg-names = "hda-reg", "video-dacs-ctrl";
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clock-names = "pix", "hddac";
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clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
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};
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};
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};
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...
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};
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1. stiH display hardware IP
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---------------------------
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The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
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- The High Quality Video Display Processor (HQVDP) gets video frames from a
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video decoder and does high quality video processing, including scaling.
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- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
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has several inputs:
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- The graphics planes are internally processed by the Generic Display
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Pipeline (GDP).
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- The video plug (VID) connects to the HQVDP output.
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- The cursor handles ... a cursor.
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- The TV OUT pre-formats (convert, clip, round) the compositor output data
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- The HDMI / DVO / HD Analog / SD analog IP builds the video signals
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- DVO (Digital Video Output) handles a 24bits parallel signal
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- The HD analog signal is typically driven by a YCbCr cable, supporting up to
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1080i mode.
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- The SD analog signal is typically used for legacy TV
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- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
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Note that some stiH drivers support only a subset of thee HW IP.
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.-------------. .-----------. .-----------.
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GPU >-------------+GDP Main | | +---+ HDMI +--> HDMI
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GPU >-------------+GDP mixer+---+ | :===========:
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GPU >-------------+Cursor | | +---+ DVO +--> 24b//
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------- | COMPOSITOR | | TV OUT | :===========:
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| | | | | +---+ HD analog +--> YCbCr
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Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
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dec | | | mixer| | +---+ SD analog +--> CVBS
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'-------' '-------------' '-----------' '-----------'
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.-----------.
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| main+--> Vsync
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| VTG |
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| aux+--> Vsync
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'-----------'
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2. DRM / HW mapping
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-------------------
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These IP are mapped to the DRM objects as following:
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- The CRTCs are mapped to the Compositor Main and Aux Mixers
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- The Framebuffers and planes are mapped to the Compositor GDP (non video
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buffers) and to HQVDP+VID (video buffers)
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- The Cursor is mapped to the Compositor Cursor
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- The Encoders are mapped to the TVOut
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- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
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FB & planes Cursor CRTC Encoders Bridges/Connectors
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| .-------------. | .-----------. .-----------. |
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+------------> |GDP | Main | | | +-> | | HDMI | <-+
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+------------> |GDP v mixer|<+ | | | :===========: |
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| |Cursor | | | +-> | | DVO | <-+
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| ------- | COMPOSITOR | | |TV OUT | | :===========: |
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| | | | | | | +-> | | HD analog | <-+
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+-> | HQVDP | |VID Aux |<+ | | | :===========: |
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| | | mixer| | +-> | | SD analog | <-+
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'-------' '-------------' '-----------' '-----------'
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