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drm/i915/bxt: Add DC9 Trigger sequence 

Add triggers for DC9 as per details provided in bxt_enable_dc9
and bxt_disable_dc9 implementations.

v1:
- Add SKL check in gen9_disable_dc5 as it is possible for DC5
  to remain disabled only for SKL.
- Add additional checks for whether DC5 is already disabled during
  DC5-disabling only for BXT.

v2:
- rebase to latest.
- Load CSR during DC9 disabling in the beginning before DC9 is
  disabled.
- Make gen9_disable_dc5 function non-static as it's being called by
  functions in i915_drv.c.
- Enable DC9-related functionality using a macro.

v3: (imre)
- remove BXT_ENABLE_DC9, we want DC9 always, and it's only valid on BXT
- remove DC5 disabling and CSR FW loaded check, these are nop atm
- squash in Vandana's "Do ddi_phy_init always" patch

v4:
- add TODO to re-enable DC5 during resume if CSR FW is available (sagar)

Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Suketu Shah 2014-11-24 13:37:45 +05:30 committed by Daniel Vetter
parent 664326f8a5
commit 31335cec02
1 changed files with 38 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/gpu/drm/i915/i915_drv.c
View File

@ -1009,6 +1009,38 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
return 0;
}
static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
/* TODO: when DC5 support is added disable DC5 here. */
broxton_ddi_phy_uninit(dev);
broxton_uninit_cdclk(dev);
bxt_enable_dc9(dev_priv);
return 0;
}
static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
/* TODO: when CSR FW support is added make sure the FW is loaded */
bxt_disable_dc9(dev_priv);
/*
* TODO: when DC5 support is added enable DC5 here if the CSR FW
* is available.
*/
broxton_init_cdclk(dev);
broxton_ddi_phy_init(dev);
intel_prepare_ddi(dev);
return 0;
}
/*
* Save all Gunit registers that may be lost after a D3 and a subsequent
* S0i[R123] transition. The list of registers needing a save/restore is
@ -1479,6 +1511,9 @@ static int intel_runtime_resume(struct device *device)
if (IS_GEN6(dev_priv))
intel_init_pch_refclk(dev);
if (IS_BROXTON(dev))
ret = bxt_resume_prepare(dev_priv);
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hsw_disable_pc8(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
@ -1511,7 +1546,9 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv->dev;
int ret;
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
if (IS_BROXTON(dev))
ret = bxt_suspend_complete(dev_priv);
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ret = hsw_suspend_complete(dev_priv);
else if (IS_VALLEYVIEW(dev))
ret = vlv_suspend_complete(dev_priv);