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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Workaround for a sparse warning in include/asm-mips/mach-tx4927/ioremap.h
  [MIPS] Make show_code static and add __user tag
  [MIPS] Workaround for a sparse warning in include/asm-mips/compat.h
  [MIPS] Add some __user tags
  [MIPS] math-emu minor cleanup
  [MIPS] Kill CONFIG_TX4927BUG_WORKAROUND
  [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_FB_XPERT98
  [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_SRC_CLK
  [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1000_USE32K
  [MIPS] Alchemy: Remove code wrapped by dead symbol CONFIG_AU1XXX_PSC_SPI
  [CHAR] Delete leftovers of old Alchemy UART driver
This commit is contained in:
Linus Torvalds 2007-07-13 10:44:45 -07:00
parent 8b69ad0e69 f24ae12b3e
commit 31c4ab430a
11 changed files with 27 additions and 100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/mips/au1000/common/setup.c
View File

@ -103,12 +103,6 @@ void __init plat_mem_setup(void)
}
#endif
#ifdef CONFIG_FB_XPERT98
if ((argptr = strstr(argptr, "video=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " video=atyfb:1024x768-8@70");
}
#endif
#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
/* au1000 does not support vra, au1500 and au1100 do */

29
arch/mips/au1000/common/time.c
View File

@ -203,11 +203,7 @@ wakeup_counter0_set(int ticks)
/* I haven't found anyone that doesn't use a 12 MHz source clock,
* but just in case.....
*/
#ifdef CONFIG_AU1000_SRC_CLK
#define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
#else
#define AU1000_SRC_CLK 12000000
#endif
/*
* We read the real processor speed from the PLL. This is important
@ -247,33 +243,8 @@ unsigned long cal_r4koff(void)
au_writel (0, SYS_TOYWRITE);
while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
#if defined(CONFIG_AU1000_USE32K)
{
unsigned long start, end, count;
start = au_readl(SYS_RTCREAD);
start += 2;
/* wait for the beginning of a new tick
*/
while (au_readl(SYS_RTCREAD) < start);
/* Start r4k counter.
*/
write_c0_count(0);
/* Wait 0.5 seconds.
*/
end = start + (32768 / trim_divide)/2;
while (end > au_readl(SYS_RTCREAD));
count = read_c0_count();
cpu_speed = count * 2;
}
#else
cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
AU1000_SRC_CLK;
#endif
}
else {
/* The 32KHz oscillator isn't running, so assume there

9
arch/mips/au1000/pb1200/board_setup.c
View File

@ -131,14 +131,7 @@ void __init board_setup(void)
/* The Pb1200 development board uses external MUX for PSC0 to
support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
*/
#if defined(CONFIG_AU1XXX_PSC_SPI) && defined(CONFIG_I2C_AU1550)
#error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
Refer to Pb1200/Db1200 documentation.
#elif defined( CONFIG_AU1XXX_PSC_SPI )
bcsr->resets |= BCSR_RESETS_PCS0MUX;
/*Hard Coding Value to enable Temp Sensors [bit 14] Value for SOC Au1200. Pls refer documentation*/
bcsr->resets =0x900f;
#elif defined( CONFIG_I2C_AU1550 )
#ifdef CONFIG_I2C_AU1550
bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
#endif
au_sync();

5
arch/mips/kernel/branch.c
View File

@ -22,7 +22,8 @@
*/
int __compute_return_epc(struct pt_regs *regs)
{
unsigned int *addr, bit, fcr31, dspcontrol;
unsigned int __user *addr;
unsigned int bit, fcr31, dspcontrol;
long epc;
union mips_instruction insn;
@ -33,7 +34,7 @@ int __compute_return_epc(struct pt_regs *regs)
/*
* Read the instruction
*/
addr = (unsigned int *) epc;
addr = (unsigned int __user *) epc;
if (__get_user(insn.word, addr)) {
force_sig(SIGSEGV, current);
return -EFAULT;

8
arch/mips/kernel/traps.c
View File

@ -131,7 +131,7 @@ static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
const int field = 2 * sizeof(unsigned long);
long stackdata;
int i;
unsigned long *sp = (unsigned long *)regs->regs[29];
unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
printk("Stack :");
i = 0;
@ -187,7 +187,7 @@ void dump_stack(void)
EXPORT_SYMBOL(dump_stack);
void show_code(unsigned int *pc)
static void show_code(unsigned int __user *pc)
{
long i;
@ -305,7 +305,7 @@ void show_registers(struct pt_regs *regs)
printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
current->comm, current->pid, current_thread_info(), current);
show_stacktrace(current, regs);
show_code((unsigned int *) regs->cp0_epc);
show_code((unsigned int __user *) regs->cp0_epc);
printk("\n");
}
@ -865,7 +865,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
dump_tlb_all();
}
show_code((unsigned int *) regs->cp0_epc);
show_code((unsigned int __user *) regs->cp0_epc);
/*
* Some chips may have other causes of machine check (e.g. SB1

19
arch/mips/math-emu/cp1emu.c
View File

@ -205,7 +205,7 @@ static int isBranchInstr(mips_instruction * i)
static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
{
mips_instruction ir;
void * emulpc, *contpc;
unsigned long emulpc, contpc;
unsigned int cond;
if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
@ -230,7 +230,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
* Linux MIPS branch emulator operates on context, updating the
* cp0_epc.
*/
emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
if (__compute_return_epc(xcp)) {
#ifdef CP1DBG
@ -244,12 +244,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
return SIGBUS;
}
/* __compute_return_epc() will have updated cp0_epc */
contpc = (void *) xcp->cp0_epc;
contpc = xcp->cp0_epc;
/* In order not to confuse ptrace() et al, tweak context */
xcp->cp0_epc = (unsigned long) emulpc - 4;
xcp->cp0_epc = emulpc - 4;
} else {
emulpc = (void *) xcp->cp0_epc;
contpc = (void *) (xcp->cp0_epc + 4);
emulpc = xcp->cp0_epc;
contpc = xcp->cp0_epc + 4;
}
emul:
@ -427,8 +427,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
* instruction
*/
xcp->cp0_epc += 4;
contpc = (void *)
(xcp->cp0_epc +
contpc = (xcp->cp0_epc +
(MIPSInst_SIMM(ir) << 2));
if (get_user(ir,
@ -462,7 +461,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
* Single step the non-cp1
* instruction in the dslot
*/
return mips_dsemul(xcp, ir, (unsigned long) contpc);
return mips_dsemul(xcp, ir, contpc);
}
else {
/* branch not taken */
@ -521,7 +520,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
}
/* we did it !! */
xcp->cp0_epc = (unsigned long) contpc;
xcp->cp0_epc = contpc;
xcp->cp0_cause &= ~CAUSEF_BD;
return 0;

12
arch/mips/math-emu/dsemul.c
View File

@ -54,8 +54,7 @@ struct emuframe {
int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
{
extern asmlinkage void handle_dsemulret(void);
mips_instruction *dsemul_insns;
struct emuframe *fr;
struct emuframe __user *fr;
int err;
if (ir == 0) { /* a nop is easy */
@ -87,8 +86,8 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
*/
/* Ensure that the two instructions are in the same cache line */
dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
fr = (struct emuframe *) dsemul_insns;
fr = (struct emuframe __user *)
((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
/* Verify that the stack pointer is not competely insane */
if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
@ -113,12 +112,13 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
int do_dsemulret(struct pt_regs *xcp)
{
struct emuframe *fr;
struct emuframe __user *fr;
unsigned long epc;
u32 insn, cookie;
int err = 0;
fr = (struct emuframe *) (xcp->cp0_epc - sizeof(mips_instruction));
fr = (struct emuframe __user *)
(xcp->cp0_epc - sizeof(mips_instruction));
/*
* If we can't even access the area, something is very wrong, but we'll

19
arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
View File

@ -138,7 +138,6 @@ extern void toshiba_rbtx4927_irq_setup(void);
char *prom_getcmdline(void);
#ifdef CONFIG_PCI
#define CONFIG_TX4927BUG_WORKAROUND
#undef TX4927_SUPPORT_COMMAND_IO
#undef TX4927_SUPPORT_PCI_66
int tx4927_cpu_clock = 100000000; /* 100MHz */
@ -669,15 +668,7 @@ void tx4927_pci_setup(void)
/* PCI->GB mappings (MEM 16MB) -not used */
tx4927_pcicptr->p2gm1plbase = 0xffffffff;
#ifdef CONFIG_TX4927BUG_WORKAROUND
/*
* TX4927-PCIC-BUG: P2GM1PUBASE must be 0
* if P2GM0PUBASE was 0.
*/
tx4927_pcicptr->p2gm1pubase = 0;
#else
tx4927_pcicptr->p2gm1pubase = 0xffffffff;
#endif
tx4927_pcicptr->p2gmgbase[1] = 0;
/* PCI->GB mappings (MEM 1MB) -not used */
@ -910,16 +901,6 @@ void __init toshiba_rbtx4927_setup(void)
if (tx4927_ccfg_toeon)
tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
/* SDRAMC fixup */
#ifdef CONFIG_TX4927BUG_WORKAROUND
/*
* TX4927-BUG: INF 01-01-18/ BUG 01-01-22
* G-bus timeout error detection is incorrect
*/
if (tx4927_ccfg_toeon)
tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */
#endif
tx4927_pci_setup();
if (tx4927_using_backplane == 1)
printk("backplane board IS installed\n");

14
drivers/char/Kconfig
View File

@ -374,20 +374,6 @@ config ISTALLION
To compile this driver as a module, choose M here: the
module will be called istallion.
config AU1000_UART
bool "Enable Au1000 UART Support"
depends on SERIAL_NONSTANDARD && MIPS
help
If you have an Alchemy AU1000 processor (MIPS based) and you want
to use serial ports, say Y. Otherwise, say N.
config AU1000_SERIAL_CONSOLE
bool "Enable Au1000 serial console"
depends on AU1000_UART
help
If you have an Alchemy AU1000 processor (MIPS based) and you want
to use a console on a serial port, say Y. Otherwise, say N.
config SERIAL_DEC
bool "DECstation serial support"
depends on MACH_DECSTATION

3
include/asm-mips/compat.h
View File

@ -132,7 +132,8 @@ typedef u32 compat_uptr_t;
static inline void __user *compat_ptr(compat_uptr_t uptr)
{
return (void __user *)(long)uptr;
/* cast to a __user pointer via "unsigned long" makes sparse happy */
return (void __user *)(unsigned long)(long)uptr;
}
static inline compat_uptr_t ptr_to_compat(void __user *uptr)

3
include/asm-mips/mach-tx49xx/ioremap.h
View File

@ -36,7 +36,8 @@ static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return (unsigned long)addr >= (unsigned long)(int)TXX9_DIRECTMAP_BASE;
return (unsigned long)addr >=
(unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff);
}
#endif /* __ASM_MACH_TX49XX_IOREMAP_H */