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[PARISC] PA7200 also supports prefetch for read 

It seems PA7200 processors also suppress traps on loads to
%r0. This means we can prefetch for read on these cpus. Of course,
we can't support prefetch for write, since that requires
LOAD DOUBLEWORD which was added with PA2.0

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Kyle McMartin 2006-08-13 20:37:26 -04:00 committed by Matthew Wilcox
parent 4068d93cd1
commit 32104b29cd
2 changed files with 4 additions and 1 deletions
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2
arch/parisc/Kconfig
View File

@ -127,7 +127,7 @@ config PA11
config PREFETCH
def_bool y
depends on PA8X00
depends on PA8X00 || PA7200
config 64BIT
bool "64-bit kernel"

3
include/asm-parisc/prefetch.h
View File

@ -24,11 +24,14 @@ extern inline void prefetch(const void *addr)
__asm__("ldw 0(%0), %%r0" : : "r" (addr));
}
/* LDD is a PA2.0 addition. */
#ifdef CONFIG_PA20
#define ARCH_HAS_PREFETCHW
extern inline void prefetchw(const void *addr)
{
__asm__("ldd 0(%0), %%r0" : : "r" (addr));
}
#endif /* CONFIG_PA20 */
#endif /* CONFIG_PREFETCH */
#endif /* __ASSEMBLY__ */