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hyperv: SVM enlightened TLB flush support flag 

Bit 22 of HYPERV_CPUID_FEATURES.EDX is specific to SVM and specifies
support for enlightened TLB flush. With this enlightenment enabled,
ASID invalidations flushes only gva->hpa entries. To flush TLB entries
derived from NPT, hypercalls should be used
(HvFlushGuestPhysicalAddressSpace or HvFlushGuestPhysicalAddressList)

Signed-off-by: Vineeth Pillai <viremana@linux.microsoft.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Message-Id: <a060f872d0df1955e52e30b877b3300485edb27c.1622730232.git.viremana@linux.microsoft.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Vineeth Pillai 2021-06-03 15:14:35 +00:00 committed by Paolo Bonzini
parent a6c776a952
commit 32431fb253
1 changed files with 9 additions and 0 deletions
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9
arch/x86/include/asm/hyperv-tlfs.h
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@ -138,6 +138,15 @@
#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
#define HV_X64_NESTED_MSR_BITMAP BIT(19)
/*
* This is specific to AMD and specifies that enlightened TLB flush is
* supported. If guest opts in to this feature, ASID invalidations only
* flushes gva -> hpa mapping entries. To flush the TLB entries derived
* from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
* or HvFlushGuestPhysicalAddressList).
*/
#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22)
/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
#define HV_PARAVISOR_PRESENT BIT(0)