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Merge commit 'fixes' into next/cleanup 

Merging in post-rc1 fixes that have gone into rc2/3 to avoid later conflicts.

* commit 'fixes': (39 commits)
  arm: dts: socfpga: Change some clocks of gate-clk type to perip-clk
  arm: socfpga: Enable ARM_TWD for socfpga
  ARM: multi_v7_defconfig: enable SDHCI_BCM_KONA and MMC_BLOCK_MINORS=16
  ARM: sunxi_defconfig: enable NFS, TMPFS, PRINTK_TIME and nfsroot support
  ARM: multi_v7_defconfig: enable network for BeagleBone Black
  ARM: dts: Fix the name of supplies for smsc911x shared by OMAP
  ARM: OMAP2+: Powerdomain: Fix unchecked dereference of arch_pwrdm
  ARM: dts: omap3-beagle: Add omap-twl4030 audio support
  ARM: dts: omap4-sdp: Fix pin muxing for wl12xx
  ARM: dts: omap4-panda-common: Fix pin muxing for wl12xx
  ARM: at91: fixed unresolved symbol "at91_pm_set_standby" when built without CONFIG_PM
  ARM: at91: add usart3 alias to dtsi
  ARM: at91: sama5d3: reduce TWI internal clock frequency
  mmc: omap: Fix I2C dependency and make driver usable with device tree
  mmc: omap: Fix DMA configuration to not rely on device id
  ARM: dts: omap3-beagle: Fix USB host on beagle boards (for 3.13)
  ARM: dts: omap3-igep0020: name twl4030 VPLL2 regulator as vdds_dsi
  ARM: dts: AM33XX IGEP0033: add USB support
  ARM: dts: AM33XX BASE0033: add 32KBit EEPROM support
  ARM: dts: AM33XX BASE0033: add pinmux and user led support
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2013-12-04 13:48:55 -08:00
parent 6316756922 a5c6e87a7b
commit 330641ceba
32 changed files with 576 additions and 115 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
Documentation/devicetree/bindings/mmc/ti-omap.txt Normal file
View File

@ -0,0 +1,54 @@
* TI MMC host controller for OMAP1 and 2420
The MMC Host Controller on TI OMAP1 and 2420 family provides
an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap mmc driver.
Note that this driver will not work with omap2430 or later omaps,
please see the omap hsmmc driver for the current omaps.
Required properties:
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
instance starting 1
Examples:
msdi1: mmc@4809c000 {
compatible = "ti,omap2420-mmc";
ti,hwmods = "msdi1";
reg = <0x4809c000 0x80>;
interrupts = <83>;
dmas = <&sdma 61 &sdma 62>;
dma-names = "tx", "rx";
};
* TI MMC host controller for OMAP1 and 2420
The MMC Host Controller on TI OMAP1 and 2420 family provides
an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap mmc driver.
Note that this driver will not work with omap2430 or later omaps,
please see the omap hsmmc driver for the current omaps.
Required properties:
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
instance starting 1
Examples:
msdi1: mmc@4809c000 {
compatible = "ti,omap2420-mmc";
ti,hwmods = "msdi1";
reg = <0x4809c000 0x80>;
interrupts = <83>;
dmas = <&sdma 61 &sdma 62>;
dma-names = "tx", "rx";
};

79
arch/arm/boot/dts/am335x-base0033.dts
View File

@ -13,4 +13,83 @@
/ { / {
model = "IGEP COM AM335x on AQUILA Expansion"; model = "IGEP COM AM335x on AQUILA Expansion";
compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_pins>;
pinctrl-1 = <&nxp_hdmi_off_pins>;
status = "okay";
};
leds_base {
pinctrl-names = "default";
pinctrl-0 = <&leds_base_pins>;
compatible = "gpio-leds";
led@0 {
label = "base:red:user";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
default-state = "off";
};
led@1 {
label = "base:green:user";
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
default-state = "off";
};
};
};
&am33xx_pinmux {
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
>;
};
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
>;
};
leds_base_pins: pinmux_leds_base_pins {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
>;
};
};
&lcdc {
status = "okay";
};
&i2c0 {
eeprom: eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
}; };

29
arch/arm/boot/dts/am335x-igep0033.dtsi
View File

@ -199,6 +199,35 @@ &uart0 {
pinctrl-0 = <&uart0_pins>; pinctrl-0 = <&uart0_pins>;
}; };
&usb {
status = "okay";
control@44e10000 {
status = "okay";
};
usb-phy@47401300 {
status = "okay";
};
usb-phy@47401b00 {
status = "okay";
};
usb@47401000 {
status = "okay";
};
usb@47401800 {
status = "okay";
dr_mode = "host";
};
dma-controller@07402000 {
status = "okay";
};
};
#include "tps65910.dtsi" #include "tps65910.dtsi"
&tps { &tps {

28
arch/arm/boot/dts/armada-370-db.dts
View File

@ -99,22 +99,22 @@ spi-flash@0 {
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
}; };
}; };
};
pcie-controller { pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay"; status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };

2
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -118,7 +118,7 @@ mpic: interrupt-controller@20000 {
coherency-fabric@20200 { coherency-fabric@20200 {
compatible = "marvell,coherency-fabric"; compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21810 0x1c>; reg = <0x20200 0xb0>, <0x21010 0x1c>;
}; };
serial@12000 { serial@12000 {

24
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -47,7 +47,7 @@ soc {
/* /*
* MV78230 has 2 PCIe units Gen2.0: One unit can be * MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is * configured as x4 or quad x1 lanes. One unit is
* x4/x1. * x1 only.
*/ */
pcie-controller { pcie-controller {
compatible = "marvell,armada-xp-pcie"; compatible = "marvell,armada-xp-pcie";
@ -62,10 +62,10 @@ pcie-controller {
ranges = ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
@ -74,8 +74,8 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 { pcie@1,0 {
device_type = "pci"; device_type = "pci";
@ -145,20 +145,20 @@ pcie@4,0 {
status = "disabled"; status = "disabled";
}; };
pcie@9,0 { pcie@5,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x4800 0 0 0 0>; reg = <0x2800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>; 0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>; interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <2>; marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 26>; clocks = <&gateclk 9>;
status = "disabled"; status = "disabled";
}; };
}; };

111
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -48,7 +48,7 @@ soc {
/* /*
* MV78260 has 3 PCIe units Gen2.0: Two units can be * MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is * configured as x4 or quad x1 lanes. One unit is
* x4/x1. * x4 only.
*/ */
pcie-controller { pcie-controller {
compatible = "marvell,armada-xp-pcie"; compatible = "marvell,armada-xp-pcie";
@ -68,7 +68,9 @@ pcie-controller {
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
@ -77,10 +79,18 @@ pcie-controller {
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 { pcie@1,0 {
device_type = "pci"; device_type = "pci";
@ -106,8 +116,8 @@ pcie@2,0 {
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>; 0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>; interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
@ -150,6 +160,74 @@ pcie@4,0 {
status = "disabled"; status = "disabled";
}; };
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
};
pcie@9,0 { pcie@9,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
@ -166,23 +244,6 @@ pcie@9,0 {
clocks = <&gateclk 26>; clocks = <&gateclk 26>;
status = "disabled"; status = "disabled";
}; };
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
}; };
internal-regs { internal-regs {

4
arch/arm/boot/dts/at91sam9x5_usart3.dtsi
View File

@ -11,6 +11,10 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
aliases {
serial4 = &usart3;
};
ahb { ahb {
apb { apb {
pinctrl@fffff400 { pinctrl@fffff400 {

4
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View File

@ -44,8 +44,8 @@ ethernet@gpmc {
gpmc,wr-access-ns = <186>; gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen; gpmc,cycle2cycle-diffcsen;
vmmc-supply = <&vddvario>; vddvario-supply = <&vddvario>;
vmmc_aux-supply = <&vdd33a>; vdd33a-supply = <&vdd33a>;
reg-io-width = <4>; reg-io-width = <4>;
smsc,save-mac-address; smsc,save-mac-address;
}; };

7
arch/arm/boot/dts/omap3-beagle-xm.dts
View File

@ -215,3 +215,10 @@ &usbhshost {
&usbhsehci { &usbhsehci {
phys = <0 &hsusb2_phy>; phys = <0 &hsusb2_phy>;
}; };
&vaux2 {
regulator-name = "usb_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

21
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -61,6 +61,14 @@ hsusb2_phy: hsusb2_phy {
vcc-supply = <&hsusb2_power>; vcc-supply = <&hsusb2_power>;
}; };
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
gpio_keys { gpio_keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
@ -120,6 +128,12 @@ twl: twl@48 {
reg = <0x48>; reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
}; };
}; };
@ -178,3 +192,10 @@ &usb_otg_hs {
mode = <3>; mode = <3>;
power = <50>; power = <50>;
}; };
&vaux2 {
regulator-name = "vdd_ehci";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};

85
arch/arm/boot/dts/omap3-igep.dtsi
View File

@ -1,5 +1,5 @@
/* /*
* Device Tree Source for IGEP Technology devices * Common device tree for IGEP boards based on AM/DM37x
* *
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@ -10,7 +10,7 @@
*/ */
/dts-v1/; /dts-v1/;
#include "omap34xx.dtsi" #include "omap36xx.dtsi"
/ { / {
memory { memory {
@ -24,6 +24,25 @@ sound {
ti,mcbsp = <&mcbsp2>; ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>; ti,codec = <&twl_audio>;
}; };
vdd33: regulator-vdd33 {
compatible = "regulator-fixed";
regulator-name = "vdd33";
regulator-always-on;
};
lbee1usjyc_vmmc: lbee1usjyc_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&lbee1usjyc_pins>;
compatible = "regulator-fixed";
regulator-name = "regulator-lbee1usjyc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
startup-delay-us = <10000>;
enable-active-high;
vin-supply = <&vdd33>;
};
}; };
&omap3_pmx_core { &omap3_pmx_core {
@ -48,6 +67,15 @@ uart3_pins: pinmux_uart3_pins {
>; >;
}; };
/* WiFi/BT combo */
lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
pinctrl-single,pins = <
0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins { mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@ -65,10 +93,17 @@ mmc1_pins: pinmux_mmc1_pins {
0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ >;
0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ };
0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */
0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
>; >;
}; };
@ -78,10 +113,33 @@ smsc911x_pins: pinmux_smsc911x_pins {
>; >;
}; };
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
>;
};
leds_pins: pinmux_leds_pins { }; leds_pins: pinmux_leds_pins { };
}; };
&i2c1 { &i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>; clock-frequency = <2600000>;
twl: twl@48 { twl: twl@48 {
@ -101,9 +159,16 @@ codec {
#include "twl4030_omap3.dtsi" #include "twl4030_omap3.dtsi"
&i2c2 { &i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
};
&mcbsp2 { &mcbsp2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>; pinctrl-0 = <&mcbsp2_pins>;
@ -114,11 +179,15 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>; pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>; vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>; vmmc_aux-supply = <&vsim>;
bus-width = <8>; bus-width = <4>;
}; };
&mmc2 { &mmc2 {
status = "disabled"; pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&lbee1usjyc_vmmc>;
bus-width = <4>;
non-removable;
}; };
&mmc3 { &mmc3 {

50
arch/arm/boot/dts/omap3-igep0020.dts
View File

@ -1,5 +1,5 @@
/* /*
* Device Tree Source for IGEPv2 board * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
* *
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@ -13,7 +13,7 @@
#include "omap-gpmc-smsc911x.dtsi" #include "omap-gpmc-smsc911x.dtsi"
/ { / {
model = "IGEPv2"; model = "IGEPv2 (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0020", "ti,omap3"; compatible = "isee,omap3-igep0020", "ti,omap3";
leds { leds {
@ -67,6 +67,8 @@ &omap3_pmx_core {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = < pinctrl-0 = <
&hsusbb1_pins &hsusbb1_pins
&tfp410_pins
&dss_pins
>; >;
hsusbb1_pins: pinmux_hsusbb1_pins { hsusbb1_pins: pinmux_hsusbb1_pins {
@ -85,6 +87,45 @@ hsusbb1_pins: pinmux_hsusbb1_pins {
0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
>; >;
}; };
tfp410_pins: tfp410_dvi_pins {
pinctrl-single,pins = <
0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
>;
};
dss_pins: pinmux_dss_dvi_pins {
pinctrl-single,pins = <
0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
}; };
&leds_pins { &leds_pins {
@ -174,3 +215,8 @@ &usbhshost {
&usbhsehci { &usbhsehci {
phys = <&hsusb1_phy>; phys = <&hsusb1_phy>;
}; };
&vpll2 {
/* Needed for DSS */
regulator-name = "vdds_dsi";
};

4
arch/arm/boot/dts/omap3-igep0030.dts
View File

@ -1,5 +1,5 @@
/* /*
* Device Tree Source for IGEP COM Module * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
* *
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@ -12,7 +12,7 @@
#include "omap3-igep.dtsi" #include "omap3-igep.dtsi"
/ { / {
model = "IGEP COM Module"; model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
compatible = "isee,omap3-igep0030", "ti,omap3"; compatible = "isee,omap3-igep0030", "ti,omap3";
leds { leds {

23
arch/arm/boot/dts/omap3-n900.dts
View File

@ -125,6 +125,21 @@ mmc1_pins: pinmux_mmc1_pins {
>; >;
}; };
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
>;
};
display_pins: pinmux_display_pins { display_pins: pinmux_display_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
@ -358,8 +373,14 @@ &mmc1 {
cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
}; };
/* most boards use vaux3, only some old versions use vmmc2 instead */
&mmc2 { &mmc2 {
status = "disabled"; pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&vaux3>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
non-removable;
}; };
&mmc3 { &mmc3 {

42
arch/arm/boot/dts/omap3.dtsi
View File

@ -82,6 +82,13 @@ ocp {
ranges; ranges;
ti,hwmods = "l3_main"; ti,hwmods = "l3_main";
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
reg = <0x480c5000 0x50>;
interrupts = <0>;
};
counter32k: counter@48320000 { counter32k: counter@48320000 {
compatible = "ti,omap-counter32k"; compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>; reg = <0x48320000 0x20>;
@ -260,6 +267,13 @@ i2c3: i2c@48060000 {
ti,hwmods = "i2c3"; ti,hwmods = "i2c3";
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap3-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
};
mcspi1: spi@48098000 { mcspi1: spi@48098000 {
compatible = "ti,omap2-mcspi"; compatible = "ti,omap2-mcspi";
reg = <0x48098000 0x100>; reg = <0x48098000 0x100>;
@ -357,6 +371,13 @@ mmc3: mmc@480ad000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mmu_isp: mmu@480bd400 {
compatible = "ti,omap3-mmu-isp";
ti,hwmods = "mmu_isp";
reg = <0x480bd400 0x80>;
interrupts = <8>;
};
wdt2: wdt@48314000 { wdt2: wdt@48314000 {
compatible = "ti,omap3-wdt"; compatible = "ti,omap3-wdt";
reg = <0x48314000 0x80>; reg = <0x48314000 0x80>;
@ -442,6 +463,27 @@ mcbsp5: mcbsp@48096000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
sham: sham@480c3000 {
compatible = "ti,omap3-sham";
ti,hwmods = "sham";
reg = <0x480c3000 0x64>;
interrupts = <49>;
};
smartreflex_core: smartreflex@480cb000 {
compatible = "ti,omap3-smartreflex-core";
ti,hwmods = "smartreflex_core";
reg = <0x480cb000 0x400>;
interrupts = <19>;
};
smartreflex_mpu_iva: smartreflex@480c9000 {
compatible = "ti,omap3-smartreflex-iva";
ti,hwmods = "smartreflex_mpu_iva";
reg = <0x480c9000 0x400>;
interrupts = <18>;
};
timer1: timer@48318000 { timer1: timer@48318000 {
compatible = "ti,omap3430-timer"; compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>; reg = <0x48318000 0x400>;

20
arch/arm/boot/dts/omap4-panda-common.dtsi
View File

@ -246,15 +246,6 @@ i2c4_pins: pinmux_i2c4_pins {
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>; >;
}; };
};
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
/* /*
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
@ -274,7 +265,7 @@ wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
@ -284,6 +275,15 @@ wl12xx_pins: pinmux_wl12xx_pins {
}; };
}; };
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>; pinctrl-0 = <&i2c1_pins>;

12
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -300,12 +300,12 @@ wl12xx_gpio: pinmux_wl12xx_gpio {
wl12xx_pins: pinmux_wl12xx_pins { wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */ 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */ 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */ 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */ 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */ 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>; >;
}; };
}; };

7
arch/arm/boot/dts/socfpga.dtsi
View File

@ -245,14 +245,14 @@ h2f_usr2_clk: h2f_usr2_clk {
mpu_periph_clk: mpu_periph_clk { mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>; clocks = <&mpuclk>;
fixed-divider = <4>; fixed-divider = <4>;
}; };
mpu_l2_ram_clk: mpu_l2_ram_clk { mpu_l2_ram_clk: mpu_l2_ram_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>; clocks = <&mpuclk>;
fixed-divider = <2>; fixed-divider = <2>;
}; };
@ -266,8 +266,9 @@ l4_main_clk: l4_main_clk {
l3_main_clk: l3_main_clk { l3_main_clk: l3_main_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>; clocks = <&mainclk>;
fixed-divider = <1>;
}; };
l3_mp_clk: l3_mp_clk { l3_mp_clk: l3_mp_clk {

3
arch/arm/configs/multi_v7_defconfig
View File

@ -69,6 +69,7 @@ CONFIG_KS8851=y
CONFIG_SMSC911X=y CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y CONFIG_STMMAC_ETH=y
CONFIG_MDIO_SUN4I=y CONFIG_MDIO_SUN4I=y
CONFIG_TI_CPSW=y
CONFIG_KEYBOARD_SPEAR=y CONFIG_KEYBOARD_SPEAR=y
CONFIG_SERIO_AMBAKMI=y CONFIG_SERIO_AMBAKMI=y
CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250=y
@ -133,12 +134,14 @@ CONFIG_USB_GPIO_VBUS=y
CONFIG_USB_ISP1301=y CONFIG_USB_ISP1301=y
CONFIG_USB_MXS_PHY=y CONFIG_USB_MXS_PHY=y
CONFIG_MMC=y CONFIG_MMC=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_ARMMMCI=y CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SDHCI_TEGRA=y
CONFIG_MMC_SDHCI_SPEAR=y CONFIG_MMC_SDHCI_SPEAR=y
CONFIG_MMC_SDHCI_BCM_KONA=y
CONFIG_MMC_OMAP=y CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS=y
CONFIG_EDAC=y CONFIG_EDAC=y

1
arch/arm/configs/omap2plus_defconfig
View File

@ -173,6 +173,7 @@ CONFIG_MFD_PALMAS=y
CONFIG_MFD_TPS65217=y CONFIG_MFD_TPS65217=y
CONFIG_MFD_TPS65910=y CONFIG_MFD_TPS65910=y
CONFIG_TWL6040_CORE=y CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_TPS65023=y CONFIG_REGULATOR_TPS65023=y
CONFIG_REGULATOR_TPS6507X=y CONFIG_REGULATOR_TPS6507X=y

7
arch/arm/configs/sunxi_defconfig
View File

@ -12,6 +12,9 @@ CONFIG_NET=y
CONFIG_PACKET=y CONFIG_PACKET=y
CONFIG_UNIX=y CONFIG_UNIX=y
CONFIG_INET=y CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_XFRM_MODE_BEET is not set
@ -58,4 +61,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_COMMON_CLK_DEBUG=y CONFIG_COMMON_CLK_DEBUG=y
# CONFIG_IOMMU_SUPPORT is not set # CONFIG_IOMMU_SUPPORT is not set
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y CONFIG_NLS=y
CONFIG_PRINTK_TIME=y

3
arch/arm/configs/u8500_defconfig
View File

@ -22,6 +22,7 @@ CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE=y
CONFIG_ARM_U8500_CPUIDLE=y
CONFIG_VFP=y CONFIG_VFP=y
CONFIG_NEON=y CONFIG_NEON=y
CONFIG_PM_RUNTIME=y CONFIG_PM_RUNTIME=y
@ -109,6 +110,8 @@ CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y CONFIG_EXT3_FS=y
CONFIG_EXT4_FS=y CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y CONFIG_VFAT_FS=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_TMPFS=y CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_POSIX_ACL=y
# CONFIG_MISC_FILESYSTEMS is not set # CONFIG_MISC_FILESYSTEMS is not set

4
arch/arm/mach-at91/pm.h
View File

@ -16,7 +16,11 @@
#include <mach/at91_ramc.h> #include <mach/at91_ramc.h>
#include <mach/at91rm9200_sdramc.h> #include <mach/at91rm9200_sdramc.h>
#ifdef CONFIG_PM
extern void at91_pm_set_standby(void (*at91_standby)(void)); extern void at91_pm_set_standby(void (*at91_standby)(void));
#else
static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
#endif
/* /*
* The AT91RM9200 goes into self-refresh mode with this command, and will * The AT91RM9200 goes into self-refresh mode with this command, and will

6
arch/arm/mach-at91/sama5d3.c
View File

@ -95,19 +95,19 @@ static struct clk twi0_clk = {
.name = "twi0_clk", .name = "twi0_clk",
.pid = SAMA5D3_ID_TWI0, .pid = SAMA5D3_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL, .type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2, .div = AT91_PMC_PCR_DIV8,
}; };
static struct clk twi1_clk = { static struct clk twi1_clk = {
.name = "twi1_clk", .name = "twi1_clk",
.pid = SAMA5D3_ID_TWI1, .pid = SAMA5D3_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL, .type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2, .div = AT91_PMC_PCR_DIV8,
}; };
static struct clk twi2_clk = { static struct clk twi2_clk = {
.name = "twi2_clk", .name = "twi2_clk",
.pid = SAMA5D3_ID_TWI2, .pid = SAMA5D3_ID_TWI2,
.type = CLK_TYPE_PERIPHERAL, .type = CLK_TYPE_PERIPHERAL,
.div = AT91_PMC_PCR_DIV2, .div = AT91_PMC_PCR_DIV8,
}; };
static struct clk mmc0_clk = { static struct clk mmc0_clk = {
.name = "mci0_clk", .name = "mci0_clk",

2
arch/arm/mach-omap2/dss-common.c
View File

@ -223,7 +223,7 @@ void __init omap_4430sdp_display_init_of(void)
static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = { static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
.name = "dvi", .name = "dvi",
.source = "tfp410.0", .source = "tfp410.0",
.i2c_bus_num = 3, .i2c_bus_num = 2,
}; };
static struct platform_device omap3_igep2_dvi_connector_device = { static struct platform_device omap3_igep2_dvi_connector_device = {

1
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -139,6 +139,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
static struct pdata_init pdata_quirks[] __initdata = { static struct pdata_init pdata_quirks[] __initdata = {
#ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3
{ "nokia,omap3-n900", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, }, { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, }, { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
{ "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },

3
arch/arm/mach-omap2/powerdomain.c
View File

@ -128,7 +128,8 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
for (i = 0; i < pwrdm->banks; i++) for (i = 0; i < pwrdm->banks; i++)
pwrdm->ret_mem_off_counter[i] = 0; pwrdm->ret_mem_off_counter[i] = 0;
arch_pwrdm->pwrdm_wait_transition(pwrdm); if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
arch_pwrdm->pwrdm_wait_transition(pwrdm);
pwrdm->state = pwrdm_read_pwrst(pwrdm); pwrdm->state = pwrdm_read_pwrst(pwrdm);
pwrdm->state_counter[pwrdm->state] = 1; pwrdm->state_counter[pwrdm->state] = 1;

1
arch/arm/mach-socfpga/Kconfig
View File

@ -10,6 +10,7 @@ config ARCH_SOCFPGA
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GPIO_PL061 if GPIOLIB select GPIO_PL061 if GPIOLIB
select HAVE_ARM_SCU select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
select HAVE_SMP select HAVE_SMP
select MFD_SYSCON select MFD_SYSCON
select SPARSE_IRQ select SPARSE_IRQ

4
arch/arm/mach-ux500/cpu-db8500.c
View File

@ -140,6 +140,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */ /* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
/* Requires DMA bindings. */ /* Requires DMA bindings. */
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
"ux500-msp-i2s.0", &msp0_platform_data), "ux500-msp-i2s.0", &msp0_platform_data),
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,

5
arch/arm/plat-omap/include/plat/dmtimer.h
View File

@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
if (timer->posted) if (timer->posted)
return; return;
if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
timer->posted = OMAP_TIMER_NONPOSTED;
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
return; return;
}
__omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
OMAP_TIMER_CTRL_POSTED, 0); OMAP_TIMER_CTRL_POSTED, 0);

45
drivers/mmc/host/omap.c
View File

@ -22,6 +22,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/of.h>
#include <linux/omap-dma.h> #include <linux/omap-dma.h>
#include <linux/mmc/host.h> #include <linux/mmc/host.h>
#include <linux/mmc/card.h> #include <linux/mmc/card.h>
@ -90,17 +91,6 @@
#define OMAP_MMC_CMDTYPE_AC 2 #define OMAP_MMC_CMDTYPE_AC 2
#define OMAP_MMC_CMDTYPE_ADTC 3 #define OMAP_MMC_CMDTYPE_ADTC 3
#define OMAP_DMA_MMC_TX 21
#define OMAP_DMA_MMC_RX 22
#define OMAP_DMA_MMC2_TX 54
#define OMAP_DMA_MMC2_RX 55
#define OMAP24XX_DMA_MMC2_TX 47
#define OMAP24XX_DMA_MMC2_RX 48
#define OMAP24XX_DMA_MMC1_TX 61
#define OMAP24XX_DMA_MMC1_RX 62
#define DRIVER_NAME "mmci-omap" #define DRIVER_NAME "mmci-omap"
/* Specifies how often in millisecs to poll for card status changes /* Specifies how often in millisecs to poll for card status changes
@ -1330,7 +1320,7 @@ static int mmc_omap_probe(struct platform_device *pdev)
struct mmc_omap_host *host = NULL; struct mmc_omap_host *host = NULL;
struct resource *res; struct resource *res;
dma_cap_mask_t mask; dma_cap_mask_t mask;
unsigned sig; unsigned sig = 0;
int i, ret = 0; int i, ret = 0;
int irq; int irq;
@ -1340,7 +1330,7 @@ static int mmc_omap_probe(struct platform_device *pdev)
} }
if (pdata->nr_slots == 0) { if (pdata->nr_slots == 0) {
dev_err(&pdev->dev, "no slots\n"); dev_err(&pdev->dev, "no slots\n");
return -ENXIO; return -EPROBE_DEFER;
} }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -1407,19 +1397,20 @@ static int mmc_omap_probe(struct platform_device *pdev)
host->dma_tx_burst = -1; host->dma_tx_burst = -1;
host->dma_rx_burst = -1; host->dma_rx_burst = -1;
if (mmc_omap2()) res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX; if (res)
else sig = res->start;
sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX; host->dma_tx = dma_request_slave_channel_compat(mask,
host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); omap_dma_filter_fn, &sig, &pdev->dev, "tx");
if (!host->dma_tx) if (!host->dma_tx)
dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
sig); sig);
if (mmc_omap2())
sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX; res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
else if (res)
sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX; sig = res->start;
host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); host->dma_rx = dma_request_slave_channel_compat(mask,
omap_dma_filter_fn, &sig, &pdev->dev, "rx");
if (!host->dma_rx) if (!host->dma_rx)
dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
sig); sig);
@ -1512,12 +1503,20 @@ static int mmc_omap_remove(struct platform_device *pdev)
return 0; return 0;
} }
#if IS_BUILTIN(CONFIG_OF)
static const struct of_device_id mmc_omap_match[] = {
{ .compatible = "ti,omap2420-mmc", },
{ },
};
#endif
static struct platform_driver mmc_omap_driver = { static struct platform_driver mmc_omap_driver = {
.probe = mmc_omap_probe, .probe = mmc_omap_probe,
.remove = mmc_omap_remove, .remove = mmc_omap_remove,
.driver = { .driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.owner = THIS_MODULE, .owner = THIS_MODULE,
.of_match_table = of_match_ptr(mmc_omap_match),
}, },
}; };