mirror of https://gitee.com/openkylin/linux.git
clk: gxbb: add MMC gate clocks, and expose for DT
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
parent
29b4817d40
commit
33608dcd01
|
@ -583,6 +583,9 @@ static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
|
|||
static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
|
||||
static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
|
||||
static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
|
||||
static MESON_GATE(emmc_a, HHI_GCLK_MPEG0, 24);
|
||||
static MESON_GATE(emmc_b, HHI_GCLK_MPEG0, 25);
|
||||
static MESON_GATE(emmc_c, HHI_GCLK_MPEG0, 26);
|
||||
static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
|
||||
|
||||
static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
|
||||
|
@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
|||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
|
|||
&gxbb_ao_ahb_bus,
|
||||
&gxbb_ao_iface,
|
||||
&gxbb_ao_i2c,
|
||||
&gxbb_emmc_a,
|
||||
&gxbb_emmc_b,
|
||||
&gxbb_emmc_c,
|
||||
};
|
||||
|
||||
static int gxbb_clkc_probe(struct platform_device *pdev)
|
||||
|
|
|
@ -172,7 +172,7 @@
|
|||
/* CLKID_CPUCLK */
|
||||
#define CLKID_HDMI_PLL 2
|
||||
#define CLKID_FIXED_PLL 3
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
/* CLKID_FCLK_DIV2 */
|
||||
#define CLKID_FCLK_DIV3 5
|
||||
#define CLKID_FCLK_DIV4 6
|
||||
#define CLKID_FCLK_DIV5 7
|
||||
|
@ -262,8 +262,11 @@
|
|||
#define CLKID_AO_AHB_BUS 91
|
||||
#define CLKID_AO_IFACE 92
|
||||
#define CLKID_AO_I2C 93
|
||||
/* CLKID_SD_EMMC_A */
|
||||
/* CLKID_SD_EMMC_B */
|
||||
/* CLKID_SD_EMMC_C */
|
||||
|
||||
#define NR_CLKS 94
|
||||
#define NR_CLKS 97
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
|
|
@ -6,7 +6,11 @@
|
|||
#define __GXBB_CLKC_H
|
||||
|
||||
#define CLKID_CPUCLK 1
|
||||
#define CLKID_FCLK_DIV2 4
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
#define CLKID_SD_EMMC_C 96
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
Loading…
Reference in New Issue