RV1108 improvements (uart-dma, clocks, interrupt numbers, gmac support

timer and emmc pins) from its first real-world user.
 RK3188 improvements (OPPv2, cpu node updates) to prepare for a new
 devicetree, the BQ Edison 2 Quad-Core.
 VPU device node for rk3288, right now only the jpeg encoder part
 will be in the kernel but hopefully other codecs will follow.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlwQw64QHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgRFJB/0WHQQtzWXEtFYxgaoWFAgkK8/Lq2LxDBTa
 aMx+slPBqMEpLOP3jfxHRy4C+dL2GX2LgaHPJN1ImwSEjUAfPsfO47LNUBl4w0Sx
 t2ulAX/TC4wz5Wa78NsGxaszHgpxmDTYeO7ue1nYJ13YlJZ2MIp/Nr9903rWve6h
 hPSzkUVe4Vuiz+KLXchzkRWS13zVhy0t9FyPyhJqzZ4ESDhS74g6cm6wuUB0XHXS
 EHvhSvgdMa8x1/2flEIXGUAScAWydiglZcraNr3LmrN6dG8PS/IhbGsxp5KCzMTZ
 DAGR47tpbXQ1N5HZEqk30yiYMDN/cNeeo2wF9nR9Df//Bj/AwnI6
 =A+kY
 -----END PGP SIGNATURE-----

Merge tag 'v4.21-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

RV1108 improvements (uart-dma, clocks, interrupt numbers, gmac support
timer and emmc pins) from its first real-world user.
RK3188 improvements (OPPv2, cpu node updates) to prepare for a new
devicetree, the BQ Edison 2 Quad-Core.
VPU device node for rk3288, right now only the jpeg encoder part
will be in the kernel but hopefully other codecs will follow.

* tag 'v4.21-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add internal timer support for rv1108
  ARM: dts: rockchip: add BQ Edison 2 QC devicetree
  ARM: dts: rockchip: add VPU device node for RK3288
  ARM: dts: rockchip: update cpu supplies on rk3188
  ARM: dts: rockchip: add phandles to secondary cpu cores
  ARM: dts: rockchip: add cpu-core resets for rk3188
  ARM: dts: rockchip: convert rk3188 to opp-v2
  ARM: dts: rockchip: add #sound-dai-cells to Cortex-A9 i2s
  ARM: dts: rockchip: Add UART DMA support for rv1108
  ARM: dts: rockchip: Assign the proper GPIO clocks for rv1108
  ARM: dts: rockchip: Fix the PMU interrupt number for rv1108
  ARM: dts: rockchip: Pass the 'arm,cpu-registers-not-fw-configured' property on rv1108
  ARM: dts: rockchip: Pass the 'clock-latency' property on rv1108
  ARM: dts: rockchip: Add rv1108 GMAC support
  ARM: dts: rockchip: add rv1108 eMMC pin settings

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-12-12 13:06:47 -08:00
commit 33afb48f32
10 changed files with 890 additions and 22 deletions

View File

@ -33,6 +33,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
- bq Edison 2 Quad-Core tablet:
Required root node properties:
- compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
- ChipSPARK Rayeager PX2 board:
Required root node properties:
- compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";

View File

@ -2,6 +2,7 @@ Rockchip rk timer
Required properties:
- compatible: should be:
"rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108
"rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036
"rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066
"rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188

View File

@ -872,6 +872,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \

View File

@ -71,6 +71,7 @@ i2s0: i2s@10118000 {
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <8>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -88,6 +89,7 @@ i2s1: i2s@1011a000 {
clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};
@ -105,6 +107,7 @@ i2s2: i2s@1011c000 {
clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};

View File

@ -0,0 +1,711 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 MundoReader S.L.
* Author: Heiko Stuebner <heiko.stuebner@bq.com>
*/
/dts-v1/;
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
/ {
model = "BQ Edison2 Quad-Core";
compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
backlight: backlight {
compatible = "pwm-backlight";
power-supply = <&vsys>;
pwms = <&pwm1 0 25000>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key &usb_int>;
power {
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
debounce-interval = <100>;
wakeup-source;
};
wake_on_usb: wake-on-usb {
label = "Wake-on-USB";
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
gpio-poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_hold>;
/* only drive the pin low until device is off */
active-delay-ms = <3000>;
};
lvds-encoder {
compatible = "ti,sn75lvds83", "lvds-encoder";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_in_vop0: endpoint {
remote-endpoint = <&vop0_out_lvds>;
};
};
port@1 {
reg = <1>;
lvds_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds>;
};
};
};
panel {
compatible = "innolux,ee101ia-01d", "panel-lvds";
backlight = <&backlight>;
/* pin LCD_CS, Nshtdn input of lvds-encoder */
enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_cs>;
power-supply = <&vcc_lcd>;
data-mapping = "vesa-24";
height-mm = <163>;
width-mm = <261>;
panel-timing {
clock-frequency = <72000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <160>;
hfront-porch = <16>;
hsync-len = <10>;
vback-porch = <23>;
vfront-porch = <12>;
vsync-len = <3>;
};
port {
panel_in_lvds: endpoint {
remote-endpoint = <&lvds_out_panel>;
};
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_reg_on>;
reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
};
avdd_cif: cif-avdd-regulator {
compatible = "regulator-fixed";
regulator-name = "avdd-cif";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cif_avdd_en>;
startup-delay-us = <100000>;
vin-supply = <&vcc28_cif>;
};
vcc_5v: vcc-5v-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&v5_drv>;
vin-supply = <&vsys>;
};
vcc_lcd: lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc-lcd";
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
startup-delay-us = <50000>;
vin-supply = <&vcc_io>;
};
vcc_otg: usb-otg-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc-otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_drv>;
startup-delay-us = <100000>;
vin-supply = <&vcc_5v>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr>;
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
vccq_emmc: emmc-vccq-regulator {
compatible = "regulator-fixed";
regulator-name = "vccq-emmc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&vcc_io>;
};
/* supplied from the bq24196 */
vsys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&cru {
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
assigned-clock-rates = <594000000>, <504000000>,
<300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vccq_emmc>;
status = "okay";
};
&gpu {
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
lis3de: accelerometer@29 {
compatible = "st,lis3de";
reg = <0x29>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB7 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&gsensor_int>;
rotation-matrix = "1", "0", "0",
"0", "-1", "0",
"0", "0", "1";
vdd-supply = <&vcc_io>;
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
tmp108@48 {
compatible = "ti,tmp108";
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tmp_alrt>;
#thermal-sensor-cells = <0>;
};
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_int>;
#clock-cells = <0>;
clock-output-names = "xin32k";
};
bat: battery@55 {
compatible = "ti,bq27541";
reg = <0x55>;
power-supplies = <&bq24196>;
};
act8846: pmic@5a {
compatible = "active-semi,act8846";
reg = <0x5a>;
pinctrl-names = "default";
pinctrl-0 = <&dvs0_ctl &pmic_int>;
vp1-supply = <&vsys>;
vp2-supply = <&vsys>;
vp3-supply = <&vsys>;
vp4-supply = <&vsys>;
inl1-supply = <&vcc_io>;
inl2-supply = <&vsys>;
inl3-supply = <&vsys>;
regulators {
vcc_ddr: REG1 {
regulator-name = "VCC_DDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_log: REG2 {
regulator-name = "VDD_LOG";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd_arm: REG3 {
regulator-name = "VDD_ARM";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
vcc_io: vcc_hdmi: REG4 {
regulator-name = "VCC_IO";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vdd_10: REG5 {
regulator-name = "VDD_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vdd_12: REG6 {
regulator-name = "VDD_12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc18_cif: REG7 {
regulator-name = "VCC18_CIF";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcca_33: REG8 {
regulator-name = "VCCA_33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcc_tp: REG9 {
regulator-name = "VCC_TP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vccio_wl: REG10 {
regulator-name = "VCCIO_WL";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
vcc_18: REG11 {
regulator-name = "VCC_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc28_cif: REG12 {
regulator-name = "VCC28_CIF";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
};
};
bq24196: charger@6b {
compatible = "ti,bq24196";
reg = <0x6b>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PD7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&charger_int &chg_ctl &otg_en>;
ti,system-minimum-microvolt = <3200000>;
monitored-battery = <&bat>;
omit-battery-class;
usb_otg_vbus: usb-otg-vbus { };
};
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
rt5616: codec@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
clocks = <&cru SCLK_I2S0>;
clock-names = "mclk";
#sound-dai-cells = <0>;
};
};
&i2s0 {
status = "okay";
};
&mmc0 {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&mmc1 {
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, <&sd1_bus4>;
vmmcq-supply = <&vccio_wl>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio3>;
interrupts = <RK_PD2 GPIO_ACTIVE_HIGH>;
interrupt-names = "host-wake";
brcm,drive-strength = <5>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake>;
};
};
&pwm1 {
status = "okay";
};
&pinctrl {
pcfg_output_high: pcfg-output-high {
output-high;
};
pcfg_output_low: pcfg-output-low {
output-low;
};
act8846 {
dvs0_ctl: dvs0-ctl {
rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>;
};
pmic_int: pmic-int {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
bq24196 {
charger_int: charger-int {
rockchip,pins = <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>;
};
/* pin hog to make it select usb profile */
chg_ctl: chg-ctl {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
};
/* low: charging, high: complete, fault: blinking */
chg_det: chg-det {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* charging enabled when pin low and register set */
chg_en: chg-en {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>;
};
/* bq29196 powergood (when low) signal */
dc_det: dc-det {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* wire bq24196 otg pin to high, to enable 500mA charging */
otg_en: otg-en {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
};
};
camera {
cif0_pdn: cif0-pdn {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
cif1_pdn: cif1-pdn {
rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
cif_avdd_en: cif-avdd-en {
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
display {
lcd_cs: lcd-cs {
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
};
lcd_en: lcd-en {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
ft5606 {
tp_int: tp-int {
rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
tp_rst: tp-rst {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi {
hdmi_int: hdmi-int {
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
hdmi_rst: hdmi-rst {
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
keys {
pwr_hold: pwr-hold {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
};
pwr_key: pwr-key {
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
lis3de {
gsensor_int: gsensor-int {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
mmc {
sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
tmp108 {
tmp_alrt: tmp-alrt {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
v5_drv: v5-drv {
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
otg_drv: otg-drv {
rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
usb_int: usb-int {
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
rk903 {
bt_host_wake: bt-host-wake {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
bt_reg_on: bt-reg-on {
rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
/* pin hog to pull the reset high */
bt_rst: bt-rst {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_output_high>;
};
bt_wake: bt-wake {
rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
wifi_host_wake: wifi-host-wake {
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
wifi_reg_on: wifi-reg-on {
rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&vcc_18>;
status = "okay";
};
&spdif {
status = "okay";
};
&uart0 {
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
device-wakeup-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake &bt_reg_on &bt_rst &bt_wake>;
};
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
status = "okay";
};
&usbphy {
status = "okay";
};
&usb_host {
status = "okay";
};
&usb_otg {
status = "okay";
};
&vop0 {
status = "okay";
};
&vop0_out {
vop0_out_lvds: endpoint {
remote-endpoint = <&lvds_in_vop0>;
};
};
&vop1 {
pinctrl-names = "default";
pinctrl-0 = <&lcdc1_dclk &lcdc1_den &lcdc1_hsync
&lcdc1_vsync &lcdc1_rgb24>;
status = "okay";
};
&wdt {
status = "okay";
};

View File

@ -44,7 +44,19 @@ vcc_sys: vsys-regulator {
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
cpu-supply = <&vdd_cpu>;
};
&cpu1 {
cpu-supply = <&vdd_cpu>;
};
&cpu2 {
cpu-supply = <&vdd_cpu>;
};
&cpu3 {
cpu-supply = <&vdd_cpu>;
};
&emmc {

View File

@ -138,7 +138,19 @@ phy0: ethernet-phy@0 {
};
&cpu0 {
cpu0-supply = <&vdd_arm>;
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&gpu {

View File

@ -23,37 +23,74 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
operating-points = <
/* kHz uV */
1608000 1350000
1416000 1250000
1200000 1150000
1008000 1075000
816000 975000
600000 950000
504000 925000
312000 875000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x1>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE1>;
};
cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x2>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE2>;
};
cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x3>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE3>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-312000000 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <875000>;
clock-latency-ns = <40000>;
};
opp-504000000 {
opp-hz = /bits/ 64 <504000000>;
opp-microvolt = <925000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
opp-suspend;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1075000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1150000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1250000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1350000>;
};
};
@ -139,6 +176,7 @@ i2s0: i2s@1011a000 {
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
rockchip,playback-channels = <2>;
rockchip,capture-channels = <2>;
#sound-dai-cells = <0>;
status = "disabled";
};

View File

@ -1232,6 +1232,18 @@ hdmi_in_vopl: endpoint@1 {
};
};
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
iommus = <&vpu_mmu>;
power-domains = <&power RK3288_PD_VIDEO>;
};
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
@ -1240,7 +1252,7 @@ vpu_mmu: iommu@ff9a0800 {
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
status = "disabled";
power-domains = <&power RK3288_PD_VIDEO>;
};
hevc_mmu: iommu@ff9c0440 {

View File

@ -32,6 +32,7 @@ cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <75>;
@ -66,13 +67,14 @@ opp-1008000000 {
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
arm,cpu-registers-not-fw-configured;
clock-frequency = <24000000>;
};
@ -117,6 +119,8 @@ uart2: serial@10210000 {
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 6>, <&pdma 7>;
#dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
@ -131,6 +135,8 @@ uart1: serial@10220000 {
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 4>, <&pdma 5>;
#dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@ -145,6 +151,8 @@ uart0: serial@10230000 {
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 2>, <&pdma 3>;
#dma-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
@ -285,6 +293,14 @@ u2phy_host: host-port {
};
};
timer: timer@10350000 {
compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
reg = <0x10350000 0x20>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>;
clock-names = "timer", "pclk";
};
watchdog: wdt@10360000 {
compatible = "snps,dw-wdt";
reg = <0x10360000 0x100>;
@ -516,6 +532,28 @@ usb_otg: usb@30180000 {
status = "disabled";
};
gmac: eth@30200000 {
compatible = "rockchip,rv1108-gmac";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&cru SCLK_MAC>,
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
clock-names = "stmmaceth",
"mac_clk_rx", "mac_clk_tx",
"clk_mac_ref", "clk_mac_refout",
"aclk_mac", "pclk_mac";
/* rv1108 only supports an rmii interface */
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins>;
rockchip,grf = <&grf>;
status = "disabled";
};
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
@ -541,7 +579,7 @@ gpio0: gpio0@20030000 {
compatible = "rockchip,gpio-bank";
reg = <0x20030000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>;
clocks = <&cru PCLK_GPIO0_PMU>;
gpio-controller;
#gpio-cells = <2>;
@ -554,7 +592,7 @@ gpio1: gpio1@10310000 {
compatible = "rockchip,gpio-bank";
reg = <0x10310000 0x100>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
@ -567,7 +605,7 @@ gpio2: gpio2@10320000 {
compatible = "rockchip,gpio-bank";
reg = <0x10320000 0x100>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
@ -580,7 +618,7 @@ gpio3: gpio3@10330000 {
compatible = "rockchip,gpio-bank";
reg = <0x10330000 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
@ -641,6 +679,42 @@ pcfg_input_high: pcfg-input-high {
input-enable;
};
emmc {
emmc_bus8: emmc-bus8 {
rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
};
gmac {
rmii_pins: rmii-pins {
rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
<1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
<1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
<1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
<1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
<1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
<1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
<1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,