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ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain 

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2015-08-04 14:28:09 +02:00 committed by Simon Horman
parent a670f3667a
commit 33c3632a3f
1 changed files with 23 additions and 0 deletions
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23
arch/arm/boot/dts/r8a7779.dtsi
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@ -173,6 +173,7 @@ i2c0: i2c@ffc70000 {
reg = <0xffc70000 0x1000>; reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>; clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -183,6 +184,7 @@ i2c1: i2c@ffc71000 {
reg = <0xffc71000 0x1000>; reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -193,6 +195,7 @@ i2c2: i2c@ffc72000 {
reg = <0xffc72000 0x1000>; reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -203,6 +206,7 @@ i2c3: i2c@ffc73000 {
reg = <0xffc73000 0x1000>; reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -212,6 +216,7 @@ scif0: serial@ffe40000 {
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -221,6 +226,7 @@ scif1: serial@ffe41000 {
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -230,6 +236,7 @@ scif2: serial@ffe42000 {
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -239,6 +246,7 @@ scif3: serial@ffe43000 {
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -248,6 +256,7 @@ scif4: serial@ffe44000 {
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -257,6 +266,7 @@ scif5: serial@ffe45000 {
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
clock-names = "sci_ick"; clock-names = "sci_ick";
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -278,6 +288,7 @@ tmu0: timer@ffd80000 {
<0 34 IRQ_TYPE_LEVEL_HIGH>; <0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>;
#renesas,channels = <3>; #renesas,channels = <3>;
@ -292,6 +303,7 @@ tmu1: timer@ffd81000 {
<0 38 IRQ_TYPE_LEVEL_HIGH>; <0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>;
#renesas,channels = <3>; #renesas,channels = <3>;
@ -306,6 +318,7 @@ tmu2: timer@ffd82000 {
<0 42 IRQ_TYPE_LEVEL_HIGH>; <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>;
#renesas,channels = <3>; #renesas,channels = <3>;
@ -317,6 +330,7 @@ sata: sata@fc600000 {
reg = <0xfc600000 0x2000>; reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>; clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>;
}; };
sdhi0: sd@ffe4c000 { sdhi0: sd@ffe4c000 {
@ -324,6 +338,7 @@ sdhi0: sd@ffe4c000 {
reg = <0xffe4c000 0x100>; reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -332,6 +347,7 @@ sdhi1: sd@ffe4d000 {
reg = <0xffe4d000 0x100>; reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -340,6 +356,7 @@ sdhi2: sd@ffe4e000 {
reg = <0xffe4e000 0x100>; reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -348,6 +365,7 @@ sdhi3: sd@ffe4f000 {
reg = <0xffe4f000 0x100>; reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -358,6 +376,7 @@ hspi0: spi@fffc7000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -368,6 +387,7 @@ hspi1: spi@fffc8000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -378,6 +398,7 @@ hspi2: spi@fffc6000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -386,6 +407,7 @@ du: display@fff80000 {
reg = <0 0xfff80000 0 0x40000>; reg = <0 0xfff80000 0 0x40000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>; clocks = <&mstp1_clks R8A7779_CLK_DU>;
power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
ports { ports {
@ -427,6 +449,7 @@ cpg_clocks: clocks@ffc80000 {
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", clock-output-names = "plla", "z", "zs", "s",
"s1", "p", "b", "out"; "s1", "p", "b", "out";
#power-domain-cells = <0>;
}; };
/* Fixed factor clocks */ /* Fixed factor clocks */