From 33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 8 Sep 2014 17:54:32 -0700 Subject: [PATCH] arm: omap: irq: define INTC_ILR0 register this is currently used as a hardcoded 0x100 offset. Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index ae082c603445..bae03290cad4 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c @@ -41,6 +41,7 @@ #define INTC_MIR_CLEAR0 0x0088 #define INTC_MIR_SET0 0x008c #define INTC_PENDING_IRQ0 0x0098 +#define INTC_ILR0 0x0100 /* Number of IRQ state bits in each MIR register */ #define IRQ_BITS_PER_REG 32