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drm/msm/dpu: remove some impossible error checking 

I'm sure there is plenty more to remove.. this is just some of the ones
I noticed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark 2019-08-22 21:00:10 -07:00
parent 15ee1e050a
commit 33e42bf6c5
6 changed files with 0 additions and 45 deletions
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19
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
View File

@ -1430,12 +1430,6 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
int pending_kickoff_cnt;
u32 ret = UINT_MAX;
if (!drm_enc || !phys) {
DPU_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
drm_enc != 0, phys != 0);
return;
}
if (!phys->hw_pp) {
DPU_ERROR("invalid pingpong hw\n");
return;
@ -1568,11 +1562,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc,
uint32_t i, pending_flush;
unsigned long lock_flags;
if (!dpu_enc) {
DPU_ERROR("invalid encoder\n");
return;
}
pending_flush = 0x0;
/* update pending counts and trigger kickoff ctl flush atomically */
@ -1800,10 +1789,6 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, bool async)
bool needs_hw_reset = false;
unsigned int i;
if (!drm_enc) {
DPU_ERROR("invalid args\n");
return;
}
dpu_enc = to_dpu_encoder_virt(drm_enc);
trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
@ -1839,10 +1824,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc, bool async)
ktime_t wakeup_time;
unsigned int i;
if (!drm_enc) {
DPU_ERROR("invalid encoder\n");
return;
}
DPU_ATRACE_BEGIN("encoder_kickoff");
dpu_enc = to_dpu_encoder_virt(drm_enc);

3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
View File

@ -720,9 +720,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank(
static void dpu_encoder_phys_cmd_handle_post_kickoff(
struct dpu_encoder_phys *phys_enc)
{
if (!phys_enc)
return;
/**
* re-enable external TE, either for the first time after enabling
* or if disabled for Autorefresh

5
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
View File

@ -612,11 +612,6 @@ static void dpu_encoder_phys_vid_handle_post_kickoff(
{
unsigned long lock_flags;
if (!phys_enc) {
DPU_ERROR("invalid encoder\n");
return;
}
/*
* Video mode must flush CTL before enabling timing engine
* Video encoders need to turn on their interfaces now

3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
View File

@ -102,9 +102,6 @@ static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
{
if (!ctx)
return 0x0;
return ctx->pending_flush_mask;
}

5
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -492,11 +492,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
int max_crtc_count;
if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) {
DPU_ERROR("invalid dpu_kms\n");
return -EINVAL;
}
dev = dpu_kms->dev;
priv = dev->dev_private;
catalog = dpu_kms->catalog;

10
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
View File

@ -265,11 +265,6 @@ void dpu_vbif_clear_errors(struct dpu_kms *dpu_kms)
struct dpu_hw_vbif *vbif;
u32 i, pnd, src;
if (!dpu_kms) {
DPU_ERROR("invalid argument\n");
return;
}
for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
vbif = dpu_kms->hw_vbif[i];
if (vbif && vbif->ops.clear_errors) {
@ -287,11 +282,6 @@ void dpu_vbif_init_memtypes(struct dpu_kms *dpu_kms)
struct dpu_hw_vbif *vbif;
int i, j;
if (!dpu_kms) {
DPU_ERROR("invalid argument\n");
return;
}
for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
vbif = dpu_kms->hw_vbif[i];
if (vbif && vbif->cap && vbif->ops.set_mem_type) {