mirror of https://gitee.com/openkylin/linux.git
iommu/vt-d: Refine the interfaces to create IRQ for DMAR unit
Refine the interfaces to create IRQ for DMAR unit. It's a preparation for converting DMAR IRQ to hierarchical irqdomain on x86. It also moves dmar_alloc_hwirq()/dmar_free_hwirq() from irq_remapping.h to dmar.h. They are not irq_remapping specific. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Sander Eikelenboom <linux@eikelenboom.it> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Vinod Koul <vinod.koul@intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Dimitri Sivanich <sivanich@sgi.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1428905519-23704-20-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -1,6 +1,4 @@
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#ifndef __IA64_INTR_REMAPPING_H
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#define __IA64_INTR_REMAPPING_H
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#define irq_remapping_enabled 0
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#define dmar_alloc_hwirq create_irq
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#define dmar_free_hwirq destroy_irq
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#endif
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@ -165,7 +165,7 @@ static struct irq_chip dmar_msi_type = {
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.irq_retrigger = ia64_msi_retrigger_irq,
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};
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static int
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static void
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msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
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{
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struct irq_cfg *cfg = irq_cfg + irq;
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@ -186,21 +186,29 @@ msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
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MSI_DATA_LEVEL_ASSERT |
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MSI_DATA_DELIVERY_FIXED |
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MSI_DATA_VECTOR(cfg->vector);
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return 0;
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}
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int arch_setup_dmar_msi(unsigned int irq)
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int dmar_alloc_hwirq(int id, int node, void *arg)
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{
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int ret;
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int irq;
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struct msi_msg msg;
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ret = msi_compose_msg(NULL, irq, &msg);
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if (ret < 0)
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return ret;
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dmar_msi_write(irq, &msg);
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irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
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"edge");
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return 0;
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irq = create_irq();
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if (irq > 0) {
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irq_set_handler_data(irq, arg);
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irq_set_chip_and_handler_name(irq, &dmar_msi_type,
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handle_edge_irq, "edge");
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msi_compose_msg(NULL, irq, &msg);
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dmar_msi_write(irq, &msg);
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}
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return irq;
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}
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void dmar_free_hwirq(int irq)
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{
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irq_set_handler_data(irq, NULL);
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destroy_irq(irq);
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}
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#endif /* CONFIG_INTEL_IOMMU */
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@ -117,8 +117,4 @@ irq_remapping_get_irq_domain(struct irq_alloc_info *info)
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#define irq_remapping_print_chip NULL
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#endif /* CONFIG_IRQ_REMAP */
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extern int dmar_alloc_hwirq(void);
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extern void dmar_free_hwirq(int irq);
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#endif /* __X86_IRQ_REMAPPING_H */
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@ -228,25 +228,27 @@ static struct irq_chip dmar_msi_type = {
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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int arch_setup_dmar_msi(unsigned int irq)
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int dmar_alloc_hwirq(int id, int node, void *arg)
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{
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int irq;
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struct msi_msg msg;
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struct irq_cfg *cfg = irq_cfg(irq);
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native_compose_msi_msg(cfg, &msg);
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dmar_msi_write(irq, &msg);
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irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
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"edge");
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return 0;
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}
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irq = irq_domain_alloc_irqs(NULL, 1, node, NULL);
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if (irq > 0) {
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irq_set_handler_data(irq, arg);
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irq_set_chip_and_handler_name(irq, &dmar_msi_type,
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handle_edge_irq, "edge");
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native_compose_msi_msg(irq_cfg(irq), &msg);
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dmar_msi_write(irq, &msg);
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}
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int dmar_alloc_hwirq(void)
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{
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return irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL);
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return irq;
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}
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void dmar_free_hwirq(int irq)
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{
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irq_set_handler_data(irq, NULL);
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irq_set_handler(irq, NULL);
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irq_domain_free_irqs(irq, 1);
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}
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#endif
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@ -1087,8 +1087,8 @@ static void free_iommu(struct intel_iommu *iommu)
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if (iommu->irq) {
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free_irq(iommu->irq, iommu);
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irq_set_handler_data(iommu->irq, NULL);
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dmar_free_hwirq(iommu->irq);
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iommu->irq = 0;
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}
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if (iommu->qi) {
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@ -1642,23 +1642,14 @@ int dmar_set_interrupt(struct intel_iommu *iommu)
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if (iommu->irq)
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return 0;
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irq = dmar_alloc_hwirq();
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if (irq <= 0) {
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irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
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if (irq > 0) {
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iommu->irq = irq;
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} else {
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pr_err("IOMMU: no free vectors\n");
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return -EINVAL;
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}
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irq_set_handler_data(irq, iommu);
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iommu->irq = irq;
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ret = arch_setup_dmar_msi(irq);
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if (ret) {
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irq_set_handler_data(irq, NULL);
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iommu->irq = 0;
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dmar_free_hwirq(irq);
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return ret;
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}
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ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
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if (ret)
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pr_err("IOMMU: can't request irq\n");
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@ -227,6 +227,7 @@ extern void dmar_msi_read(int irq, struct msi_msg *msg);
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extern void dmar_msi_write(int irq, struct msi_msg *msg);
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extern int dmar_set_interrupt(struct intel_iommu *iommu);
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extern irqreturn_t dmar_fault(int irq, void *dev_id);
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extern int arch_setup_dmar_msi(unsigned int irq);
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extern int dmar_alloc_hwirq(int id, int node, void *arg);
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extern void dmar_free_hwirq(int irq);
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#endif /* __DMAR_H__ */
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