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sparc32: remove cast from output constraints in math asm statements 

The following asm statements generated a sparse warning:

        asm("addcc \n\t" : "=r" (((USItype)(r2)))

warning: asm output is not an lvalue

When asking on the sparse mailing list Linus replyed:

"
Those casts to (USItype) are all pointless to begin with (since the
values are of that type already!) and they mean that the expression
isn't something you can assign to (lvalue).
"

In the math emulation code drop all casts in the output
parts of the asm statements.

This fixes a lot of "warning: asm output is not an lvalue" sparse
warnings in math_32.c.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sam Ravnborg 2014-05-16 23:25:46 +02:00 committed by David S. Miller
parent 958b7b0720
commit 347b0cf022
2 changed files with 24 additions and 24 deletions
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28
arch/sparc/include/asm/sfp-machine_32.h
View File

@ -79,9 +79,9 @@
__asm__ ("addcc %r7,%8,%2\n\t" \
"addxcc %r5,%6,%1\n\t" \
"addx %r3,%4,%0\n" \
: "=r" ((USItype)(r2)), \
"=&r" ((USItype)(r1)), \
"=&r" ((USItype)(r0)) \
: "=r" (r2), \
"=&r" (r1), \
"=&r" (r0) \
: "%rJ" ((USItype)(x2)), \
"rI" ((USItype)(y2)), \
"%rJ" ((USItype)(x1)), \
@ -94,9 +94,9 @@
__asm__ ("subcc %r7,%8,%2\n\t" \
"subxcc %r5,%6,%1\n\t" \
"subx %r3,%4,%0\n" \
: "=r" ((USItype)(r2)), \
"=&r" ((USItype)(r1)), \
"=&r" ((USItype)(r0)) \
: "=r" (r2), \
"=&r" (r1), \
"=&r" (r0) \
: "%rJ" ((USItype)(x2)), \
"rI" ((USItype)(y2)), \
"%rJ" ((USItype)(x1)), \
@ -115,8 +115,8 @@
"addxcc %r6,%7,%0\n\t" \
"addxcc %r4,%5,%%g2\n\t" \
"addx %r2,%3,%%g1\n\t" \
: "=&r" ((USItype)(r1)), \
"=&r" ((USItype)(r0)) \
: "=&r" (r1), \
"=&r" (r0) \
: "%rJ" ((USItype)(x3)), \
"rI" ((USItype)(y3)), \
"%rJ" ((USItype)(x2)), \
@ -140,8 +140,8 @@
"subxcc %r6,%7,%0\n\t" \
"subxcc %r4,%5,%%g2\n\t" \
"subx %r2,%3,%%g1\n\t" \
: "=&r" ((USItype)(r1)), \
"=&r" ((USItype)(r0)) \
: "=&r" (r1), \
"=&r" (r0) \
: "%rJ" ((USItype)(x3)), \
"rI" ((USItype)(y3)), \
"%rJ" ((USItype)(x2)), \
@ -164,10 +164,10 @@
"addxcc %2,%%g0,%2\n\t" \
"addxcc %1,%%g0,%1\n\t" \
"addx %0,%%g0,%0\n\t" \
: "=&r" ((USItype)(x3)), \
"=&r" ((USItype)(x2)), \
"=&r" ((USItype)(x1)), \
"=&r" ((USItype)(x0)) \
: "=&r" (x3), \
"=&r" (x2), \
"=&r" (x1), \
"=&r" (x0) \
: "rI" ((USItype)(i)), \
"0" ((USItype)(x3)), \
"1" ((USItype)(x2)), \

20
arch/sparc/math-emu/sfp-util_32.h
View File

@ -4,20 +4,20 @@
#include <asm/byteorder.h>
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\t" \
__asm__ ("addcc %r4,%5,%1\n\t" \
"addx %r2,%3,%0\n" \
: "=r" ((USItype)(sh)), \
"=&r" ((USItype)(sl)) \
: "=r" (sh), \
"=&r" (sl) \
: "%rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"%rJ" ((USItype)(al)), \
"rI" ((USItype)(bl)) \
: "cc")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\t" \
__asm__ ("subcc %r4,%5,%1\n\t" \
"subx %r2,%3,%0\n" \
: "=r" ((USItype)(sh)), \
"=&r" ((USItype)(sl)) \
: "=r" (sh), \
"=&r" (sl) \
: "rJ" ((USItype)(ah)), \
"rI" ((USItype)(bh)), \
"rJ" ((USItype)(al)), \
@ -65,8 +65,8 @@
"mulscc %%g1,0,%%g1\n\t" \
"add %%g1,%%g2,%0\n\t" \
"rd %%y,%1\n" \
: "=r" ((USItype)(w1)), \
"=r" ((USItype)(w0)) \
: "=r" (w1), \
"=r" (w0) \
: "%rI" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "%g1", "%g2", "cc")
@ -98,8 +98,8 @@
"sub %1,%2,%1\n\t" \
"3: xnor %0,0,%0\n\t" \
"! End of inline udiv_qrnnd\n" \
: "=&r" ((USItype)(q)), \
"=&r" ((USItype)(r)) \
: "=&r" (q), \
"=&r" (r) \
: "r" ((USItype)(d)), \
"1" ((USItype)(n1)), \
"0" ((USItype)(n0)) : "%g1", "cc")