mirror of https://gitee.com/openkylin/linux.git
sparc32: drop unused atomic24 support
atomic24 support was used to semaphores in the past - but is no longer used. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sam Ravnborg
David S. Miller
parent
371de6e4e0
commit
348738afe5
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@ -52,106 +52,6 @@ extern void atomic_set(atomic_t *, int);
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
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/* This is the old 24-bit implementation. It's still used internally
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* by some sparc-specific code, notably the semaphore implementation.
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*/
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typedef struct { volatile int counter; } atomic24_t;
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#ifndef CONFIG_SMP
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#define ATOMIC24_INIT(i) { (i) }
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#define atomic24_read(v) ((v)->counter)
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#define atomic24_set(v, i) (((v)->counter) = i)
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#else
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/* We do the bulk of the actual work out of line in two common
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* routines in assembler, see arch/sparc/lib/atomic.S for the
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* "fun" details.
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*
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* For SMP the trick is you embed the spin lock byte within
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* the word, use the low byte so signedness is easily retained
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* via a quick arithmetic shift. It looks like this:
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*
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* ----------------------------------------
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* | signed 24-bit counter value | lock | atomic_t
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* ----------------------------------------
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* 31 8 7 0
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*/
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#define ATOMIC24_INIT(i) { ((i) << 8) }
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static inline int atomic24_read(const atomic24_t *v)
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{
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int ret = v->counter;
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while(ret & 0xff)
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ret = v->counter;
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return ret >> 8;
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}
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#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
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#endif
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static inline int __atomic24_add(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_add\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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static inline int __atomic24_sub(int i, atomic24_t *v)
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{
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register volatile int *ptr asm("g1");
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register int increment asm("g2");
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register int tmp1 asm("g3");
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register int tmp2 asm("g4");
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register int tmp3 asm("g7");
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ptr = &v->counter;
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increment = i;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___atomic24_sub\n\t"
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" add %%o7, 8, %%o7\n"
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: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
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: "0" (increment), "r" (ptr)
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: "memory", "cc");
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return increment;
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}
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#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
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#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
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#define atomic24_dec_return(v) __atomic24_sub(1, (v))
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#define atomic24_inc_return(v) __atomic24_add(1, (v))
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#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
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#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
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#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
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#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
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#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
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/* Atomic operations are already serializing */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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@ -40,60 +40,5 @@ ___xchg32_sun4md:
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mov %g4, %o7
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#endif
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/* Read asm-sparc/atomic.h carefully to understand how this works for SMP.
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* Really, some things here for SMP are overly clever, go read the header.
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*/
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.globl ___atomic24_add
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___atomic24_add:
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rd %psr, %g3 ! Keep the code small, old way was stupid
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nop; nop; nop; ! Let the bits set
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or %g3, PSR_PIL, %g7 ! Disable interrupts
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wr %g7, 0x0, %psr ! Set %psr
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nop; nop; nop; ! Let the bits set
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#ifdef CONFIG_SMP
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1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
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orcc %g7, 0x0, %g0 ! Did we get it?
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bne 1b ! Nope...
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ld [%g1], %g7 ! Load locked atomic24_t
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sra %g7, 8, %g7 ! Get signed 24-bit integer
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add %g7, %g2, %g2 ! Add in argument
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sll %g2, 8, %g7 ! Transpose back to atomic24_t
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st %g7, [%g1] ! Clever: This releases the lock as well.
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#else
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ld [%g1], %g7 ! Load locked atomic24_t
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add %g7, %g2, %g2 ! Add in argument
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st %g2, [%g1] ! Store it back
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#endif
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wr %g3, 0x0, %psr ! Restore original PSR_PIL
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nop; nop; nop; ! Let the bits set
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jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
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mov %g4, %o7 ! Restore %o7
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.globl ___atomic24_sub
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___atomic24_sub:
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rd %psr, %g3 ! Keep the code small, old way was stupid
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nop; nop; nop; ! Let the bits set
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or %g3, PSR_PIL, %g7 ! Disable interrupts
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wr %g7, 0x0, %psr ! Set %psr
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nop; nop; nop; ! Let the bits set
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#ifdef CONFIG_SMP
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1: ldstub [%g1 + 3], %g7 ! Spin on the byte lock for SMP.
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orcc %g7, 0x0, %g0 ! Did we get it?
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bne 1b ! Nope...
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ld [%g1], %g7 ! Load locked atomic24_t
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sra %g7, 8, %g7 ! Get signed 24-bit integer
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sub %g7, %g2, %g2 ! Subtract argument
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sll %g2, 8, %g7 ! Transpose back to atomic24_t
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st %g7, [%g1] ! Clever: This releases the lock as well
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#else
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ld [%g1], %g7 ! Load locked atomic24_t
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sub %g7, %g2, %g2 ! Subtract argument
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st %g2, [%g1] ! Store it back
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#endif
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wr %g3, 0x0, %psr ! Restore original PSR_PIL
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nop; nop; nop; ! Let the bits set
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jmpl %o7, %g0 ! NOTE: not + 8, see callers in atomic.h
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mov %g4, %o7 ! Restore %o7
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.globl __atomic_end
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__atomic_end:
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@ -62,8 +62,6 @@ extern void ___rw_read_enter(void);
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extern void ___rw_read_try(void);
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extern void ___rw_read_exit(void);
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extern void ___rw_write_enter(void);
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extern void ___atomic24_add(void);
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extern void ___atomic24_sub(void);
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/* Alias functions whose names begin with "." and export the aliases.
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* The module references will be fixed up by module_frob_arch_sections.
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@ -97,10 +95,6 @@ EXPORT_SYMBOL(___rw_read_exit);
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EXPORT_SYMBOL(___rw_write_enter);
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#endif
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/* Atomic operations. */
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EXPORT_SYMBOL(___atomic24_add);
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EXPORT_SYMBOL(___atomic24_sub);
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EXPORT_SYMBOL(__ashrdi3);
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EXPORT_SYMBOL(__ashldi3);
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EXPORT_SYMBOL(__lshrdi3);
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