mirror of https://gitee.com/openkylin/linux.git
arm64: dts: juno/rtsm: re-structure motherboard includes
It is a bit unorthodox to just include a file in the middle of a another DTS file, it breaks the pattern from other device trees and also makes it really hard to reference things across the files with phandles. Restructure the include for the Juno/RTSM motherboards to happen at the top of the file, reference the target nodes directly, and indent the motherboard .dtsi files to reflect their actual depth in the hierarchy. This is a purely syntactic change that result in the same DTB files from the DTS/DTSI files. This is based on similar patch from Linus Walleij for ARM Vexpress platforms. Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Sudeep Holla
parent
506eeeabb5
commit
349b0f95e1
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@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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// SPDX-License-Identifier: GPL-2.0
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#include "juno-clocks.dtsi"
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#include "juno-clocks.dtsi"
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#include "juno-motherboard.dtsi"
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/ {
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/ {
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/*
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/*
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@ -795,8 +796,6 @@ smb@8000000 {
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<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic 0 0 0 167 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic 0 0 0 168 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
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<0 0 12 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>;
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/include/ "juno-motherboard.dtsi"
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};
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};
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site2: tlx@60000000 {
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site2: tlx@60000000 {
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@ -7,6 +7,8 @@
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*
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*
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*/
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*/
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/ {
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smb@8000000 {
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mb_clk24mhz: clk24mhz {
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mb_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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compatible = "fixed-clock";
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#clock-cells = <0>;
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#clock-cells = <0>;
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@ -287,3 +289,5 @@ iofpga_gpio0: gpio@1d0000 {
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};
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};
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};
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};
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};
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};
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};
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};
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@ -12,6 +12,8 @@
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/memreserve/ 0x80000000 0x00010000;
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/memreserve/ 0x80000000 0x00010000;
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#include "rtsm_ve-motherboard.dtsi"
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/ {
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/ {
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model = "RTSM_VE_AEMv8A";
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model = "RTSM_VE_AEMv8A";
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compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
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compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
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@ -162,7 +164,5 @@ smb@8000000 {
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<0 0 40 &gic 0 40 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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<0 0 42 &gic 0 42 4>;
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/include/ "rtsm_ve-motherboard.dtsi"
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};
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};
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};
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};
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@ -7,270 +7,273 @@
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*
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*
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* VEMotherBoard.lisa
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* VEMotherBoard.lisa
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*/
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*/
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/ {
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motherboard {
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smb@8000000 {
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arm,v2m-memory-map = "rs1";
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motherboard {
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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arm,v2m-memory-map = "rs1";
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#address-cells = <2>; /* SMB chipselect number and offset */
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compatible = "arm,vexpress,v2m-p1", "simple-bus";
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#size-cells = <1>;
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#address-cells = <2>; /* SMB chipselect number and offset */
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#interrupt-cells = <1>;
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ranges;
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flash@0,00000000 {
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0 0x00000000 0x04000000>,
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<4 0x00000000 0x04000000>;
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bank-width = <4>;
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};
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v2m_video_ram: vram@2,00000000 {
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compatible = "arm,vexpress-vram";
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reg = <2 0x00000000 0x00800000>;
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};
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ethernet@2,02000000 {
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compatible = "smsc,lan91c111";
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reg = <2 0x02000000 0x10000>;
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interrupts = <15>;
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};
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v2m_clk24mhz: clk24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "v2m:clk24mhz";
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};
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v2m_refclk1mhz: refclk1mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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clock-output-names = "v2m:refclk1mhz";
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};
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v2m_refclk32khz: refclk32khz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "v2m:refclk32khz";
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};
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iofpga@3,00000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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ranges = <0 3 0 0x200000>;
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#interrupt-cells = <1>;
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ranges;
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v2m_sysreg: sysreg@10000 {
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flash@0,00000000 {
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compatible = "arm,vexpress-sysreg";
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compatible = "arm,vexpress-flash", "cfi-flash";
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reg = <0x010000 0x1000>;
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reg = <0 0x00000000 0x04000000>,
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gpio-controller;
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<4 0x00000000 0x04000000>;
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#gpio-cells = <2>;
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bank-width = <4>;
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};
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};
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v2m_sysctl: sysctl@20000 {
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v2m_video_ram: vram@2,00000000 {
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compatible = "arm,sp810", "arm,primecell";
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compatible = "arm,vexpress-vram";
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reg = <0x020000 0x1000>;
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reg = <2 0x00000000 0x00800000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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};
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aaci@40000 {
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ethernet@2,02000000 {
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compatible = "arm,pl041", "arm,primecell";
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compatible = "smsc,lan91c111";
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reg = <0x040000 0x1000>;
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reg = <2 0x02000000 0x10000>;
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interrupts = <11>;
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interrupts = <15>;
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clocks = <&v2m_clk24mhz>;
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clock-names = "apb_pclk";
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};
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};
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mmci@50000 {
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v2m_clk24mhz: clk24mhz {
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compatible = "arm,pl180", "arm,primecell";
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compatible = "fixed-clock";
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reg = <0x050000 0x1000>;
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#clock-cells = <0>;
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interrupts = <9 10>;
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clock-frequency = <24000000>;
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cd-gpios = <&v2m_sysreg 0 0>;
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clock-output-names = "v2m:clk24mhz";
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wp-gpios = <&v2m_sysreg 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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};
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kmi@60000 {
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v2m_refclk1mhz: refclk1mhz {
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compatible = "arm,pl050", "arm,primecell";
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compatible = "fixed-clock";
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reg = <0x060000 0x1000>;
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#clock-cells = <0>;
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interrupts = <12>;
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clock-frequency = <1000000>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-output-names = "v2m:refclk1mhz";
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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};
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kmi@70000 {
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v2m_refclk32khz: refclk32khz {
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compatible = "arm,pl050", "arm,primecell";
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compatible = "fixed-clock";
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reg = <0x070000 0x1000>;
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#clock-cells = <0>;
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interrupts = <13>;
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clock-frequency = <32768>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-output-names = "v2m:refclk32khz";
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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};
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v2m_serial0: uart@90000 {
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iofpga@3,00000000 {
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compatible = "arm,pl011", "arm,primecell";
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compatible = "simple-bus";
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reg = <0x090000 0x1000>;
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#address-cells = <1>;
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interrupts = <5>;
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#size-cells = <1>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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ranges = <0 3 0 0x200000>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a0000 {
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v2m_sysreg: sysreg@10000 {
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compatible = "arm,pl011", "arm,primecell";
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compatible = "arm,vexpress-sysreg";
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reg = <0x0a0000 0x1000>;
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reg = <0x010000 0x1000>;
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interrupts = <6>;
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gpio-controller;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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#gpio-cells = <2>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial2: uart@b0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0b0000 0x1000>;
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interrupts = <7>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial3: uart@c0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0c0000 0x1000>;
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interrupts = <8>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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wdt@f0000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0f0000 0x1000>;
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interrupts = <0>;
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clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
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clock-names = "wdogclk", "apb_pclk";
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};
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v2m_timer01: timer@110000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x110000 0x1000>;
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interrupts = <2>;
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clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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v2m_timer23: timer@120000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x120000 0x1000>;
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interrupts = <3>;
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clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
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clock-names = "timclken1", "timclken2", "apb_pclk";
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};
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rtc@170000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x170000 0x1000>;
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interrupts = <4>;
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clocks = <&v2m_clk24mhz>;
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clock-names = "apb_pclk";
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};
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clcd@1f0000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x1f0000 0x1000>;
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interrupt-names = "combined";
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interrupts = <14>;
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clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
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clock-names = "clcdclk", "apb_pclk";
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arm,pl11x,framebuffer = <0x18000000 0x00180000>;
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memory-region = <&v2m_video_ram>;
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max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
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port {
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v2m_clcd_pads: endpoint {
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remote-endpoint = <&v2m_clcd_panel>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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};
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panel {
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v2m_sysctl: sysctl@20000 {
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compatible = "panel-dpi";
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compatible = "arm,sp810", "arm,primecell";
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reg = <0x020000 0x1000>;
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clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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clock-names = "refclk", "timclk", "apb_pclk";
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#clock-cells = <1>;
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clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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};
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aaci@40000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x040000 0x1000>;
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interrupts = <11>;
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clocks = <&v2m_clk24mhz>;
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clock-names = "apb_pclk";
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};
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mmci@50000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x050000 0x1000>;
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interrupts = <9 10>;
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cd-gpios = <&v2m_sysreg 0 0>;
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wp-gpios = <&v2m_sysreg 1 0>;
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max-frequency = <12000000>;
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vmmc-supply = <&v2m_fixed_3v3>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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kmi@60000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x060000 0x1000>;
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interrupts = <12>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@70000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x070000 0x1000>;
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interrupts = <13>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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v2m_serial0: uart@90000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x090000 0x1000>;
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interrupts = <5>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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v2m_serial1: uart@a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0a0000 0x1000>;
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interrupts = <6>;
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clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
|
||||||
|
|
||||||
|
v2m_serial2: uart@b0000 {
|
||||||
|
compatible = "arm,pl011", "arm,primecell";
|
||||||
|
reg = <0x0b0000 0x1000>;
|
||||||
|
interrupts = <7>;
|
||||||
|
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "uartclk", "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
v2m_serial3: uart@c0000 {
|
||||||
|
compatible = "arm,pl011", "arm,primecell";
|
||||||
|
reg = <0x0c0000 0x1000>;
|
||||||
|
interrupts = <8>;
|
||||||
|
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "uartclk", "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
wdt@f0000 {
|
||||||
|
compatible = "arm,sp805", "arm,primecell";
|
||||||
|
reg = <0x0f0000 0x1000>;
|
||||||
|
interrupts = <0>;
|
||||||
|
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "wdogclk", "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
v2m_timer01: timer@110000 {
|
||||||
|
compatible = "arm,sp804", "arm,primecell";
|
||||||
|
reg = <0x110000 0x1000>;
|
||||||
|
interrupts = <2>;
|
||||||
|
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
v2m_timer23: timer@120000 {
|
||||||
|
compatible = "arm,sp804", "arm,primecell";
|
||||||
|
reg = <0x120000 0x1000>;
|
||||||
|
interrupts = <3>;
|
||||||
|
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "timclken1", "timclken2", "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@170000 {
|
||||||
|
compatible = "arm,pl031", "arm,primecell";
|
||||||
|
reg = <0x170000 0x1000>;
|
||||||
|
interrupts = <4>;
|
||||||
|
clocks = <&v2m_clk24mhz>;
|
||||||
|
clock-names = "apb_pclk";
|
||||||
|
};
|
||||||
|
|
||||||
|
clcd@1f0000 {
|
||||||
|
compatible = "arm,pl111", "arm,primecell";
|
||||||
|
reg = <0x1f0000 0x1000>;
|
||||||
|
interrupt-names = "combined";
|
||||||
|
interrupts = <14>;
|
||||||
|
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
|
||||||
|
clock-names = "clcdclk", "apb_pclk";
|
||||||
|
arm,pl11x,framebuffer = <0x18000000 0x00180000>;
|
||||||
|
memory-region = <&v2m_video_ram>;
|
||||||
|
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
|
||||||
|
|
||||||
port {
|
port {
|
||||||
v2m_clcd_panel: endpoint {
|
v2m_clcd_pads: endpoint {
|
||||||
remote-endpoint = <&v2m_clcd_pads>;
|
remote-endpoint = <&v2m_clcd_panel>;
|
||||||
|
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
panel-timing {
|
panel {
|
||||||
clock-frequency = <63500127>;
|
compatible = "panel-dpi";
|
||||||
hactive = <1024>;
|
|
||||||
hback-porch = <152>;
|
port {
|
||||||
hfront-porch = <48>;
|
v2m_clcd_panel: endpoint {
|
||||||
hsync-len = <104>;
|
remote-endpoint = <&v2m_clcd_pads>;
|
||||||
vactive = <768>;
|
};
|
||||||
vback-porch = <23>;
|
};
|
||||||
vfront-porch = <3>;
|
|
||||||
vsync-len = <4>;
|
panel-timing {
|
||||||
|
clock-frequency = <63500127>;
|
||||||
|
hactive = <1024>;
|
||||||
|
hback-porch = <152>;
|
||||||
|
hfront-porch = <48>;
|
||||||
|
hsync-len = <104>;
|
||||||
|
vactive = <768>;
|
||||||
|
vback-porch = <23>;
|
||||||
|
vfront-porch = <3>;
|
||||||
|
vsync-len = <4>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
virtio-block@130000 {
|
||||||
|
compatible = "virtio,mmio";
|
||||||
|
reg = <0x130000 0x200>;
|
||||||
|
interrupts = <42>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
virtio-block@130000 {
|
v2m_fixed_3v3: v2m-3v3 {
|
||||||
compatible = "virtio,mmio";
|
compatible = "regulator-fixed";
|
||||||
reg = <0x130000 0x200>;
|
regulator-name = "3V3";
|
||||||
interrupts = <42>;
|
regulator-min-microvolt = <3300000>;
|
||||||
};
|
regulator-max-microvolt = <3300000>;
|
||||||
};
|
regulator-always-on;
|
||||||
|
|
||||||
v2m_fixed_3v3: v2m-3v3 {
|
|
||||||
compatible = "regulator-fixed";
|
|
||||||
regulator-name = "3V3";
|
|
||||||
regulator-min-microvolt = <3300000>;
|
|
||||||
regulator-max-microvolt = <3300000>;
|
|
||||||
regulator-always-on;
|
|
||||||
};
|
|
||||||
|
|
||||||
mcc {
|
|
||||||
compatible = "arm,vexpress,config-bus";
|
|
||||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
|
||||||
|
|
||||||
v2m_oscclk1: oscclk1 {
|
|
||||||
/* CLCD clock */
|
|
||||||
compatible = "arm,vexpress-osc";
|
|
||||||
arm,vexpress-sysreg,func = <1 1>;
|
|
||||||
freq-range = <23750000 63500000>;
|
|
||||||
#clock-cells = <0>;
|
|
||||||
clock-output-names = "v2m:oscclk1";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
reset {
|
mcc {
|
||||||
compatible = "arm,vexpress-reset";
|
compatible = "arm,vexpress,config-bus";
|
||||||
arm,vexpress-sysreg,func = <5 0>;
|
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||||
};
|
|
||||||
|
|
||||||
muxfpga {
|
v2m_oscclk1: oscclk1 {
|
||||||
compatible = "arm,vexpress-muxfpga";
|
/* CLCD clock */
|
||||||
arm,vexpress-sysreg,func = <7 0>;
|
compatible = "arm,vexpress-osc";
|
||||||
};
|
arm,vexpress-sysreg,func = <1 1>;
|
||||||
|
freq-range = <23750000 63500000>;
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-output-names = "v2m:oscclk1";
|
||||||
|
};
|
||||||
|
|
||||||
shutdown {
|
reset {
|
||||||
compatible = "arm,vexpress-shutdown";
|
compatible = "arm,vexpress-reset";
|
||||||
arm,vexpress-sysreg,func = <8 0>;
|
arm,vexpress-sysreg,func = <5 0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
reboot {
|
muxfpga {
|
||||||
compatible = "arm,vexpress-reboot";
|
compatible = "arm,vexpress-muxfpga";
|
||||||
arm,vexpress-sysreg,func = <9 0>;
|
arm,vexpress-sysreg,func = <7 0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
dvimode {
|
shutdown {
|
||||||
compatible = "arm,vexpress-dvimode";
|
compatible = "arm,vexpress-shutdown";
|
||||||
arm,vexpress-sysreg,func = <11 0>;
|
arm,vexpress-sysreg,func = <8 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reboot {
|
||||||
|
compatible = "arm,vexpress-reboot";
|
||||||
|
arm,vexpress-sysreg,func = <9 0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
dvimode {
|
||||||
|
compatible = "arm,vexpress-dvimode";
|
||||||
|
arm,vexpress-sysreg,func = <11 0>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
};
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue