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Merge branch 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux 

* 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux: (98 commits)
  Input: s3c24xx_ts - depend on SAMSUNG_DEV_TS and update menu entry
  Input: s3c24xx_ts - Add FEAT for Samsung touchscreen support
  Input: s3c24xx_ts - Implement generic GPIO configuration callback
  ARM: SAMSUNG: Move s3c64xx dev-ts.c to plat-samsung and rename configuration
  ARM: SAMSUNG: Implements cfg_gpio function for Samsung touchscreen
  ARM: S3C64XX: Add touchscreen platform device definition
  ARM: SAMSUNG: Move mach/ts.h to plat/ts.h
  ARM: S5PC100: Move i2c helpers from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: Move frame buffer helpers from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: gpio.h cleanup
  ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: Use common functions for gpiolib implementation
  drivers: serial: S5PC100 serial driver cleanup
  ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move
  ARM: SAMSUNG: Copy common I2C0 device helpers to machine directories
  ARM: SAMSUNG: move driver strength gpio configuration helper to common dir
  ARM: S5PV210: Add GPIOlib support
  ARM: SAMSUNGy: fix broken timer irq base
  ARM: SMDK6440: Add audio devices on board
  ARM: S5P6440: Add audio platform devices
  ...
This commit is contained in:
Linus Torvalds 2010-05-19 11:49:33 -07:00
parent fa9dc265ac 504d36e91a
commit 349e1fba7e
124 changed files with 6828 additions and 896 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Makefile
View File

@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__
head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
textofs-y := 0x00008000
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000

9
arch/arm/mach-s3c2410/Kconfig
View File

@ -77,6 +77,7 @@ config ARCH_H1940
select PM_H1940 if PM
select S3C_DEV_USB_HOST
select S3C_DEV_NAND
select S3C2410_SETUP_TS
help
Say Y here if you are using the HP IPAQ H1940
@ -96,12 +97,19 @@ config PM_H1940
config MACH_N30
bool "Acer N30 family"
select CPU_S3C2410
select MACH_N35
select S3C_DEV_USB_HOST
select S3C_DEV_NAND
help
Say Y here if you want suppt for the Acer N30, Acer N35,
Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
config MACH_N35
bool
help
Internal node in order to enable support for Acer N35 if Acer N30 is
selected.
config ARCH_BAST
bool "Simtec Electronics BAST (EB2410ITX)"
select CPU_S3C2410
@ -111,6 +119,7 @@ config ARCH_BAST
select MACH_BAST_IDE
select S3C24XX_DCLK
select ISA
select S3C_DEV_HWMON
select S3C_DEV_USB_HOST
select S3C_DEV_NAND
help

10
arch/arm/mach-s3c2410/Makefile.boot
View File

@ -1,3 +1,7 @@
zreladdr-y := 0x30008000
params_phys-y := 0x30000100
ifeq ($(CONFIG_PM_H1940),y)
zreladdr-y := 0x30108000
params_phys-y := 0x30100100
else
zreladdr-y := 0x30008000
params_phys-y := 0x30000100
endif

25
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
View File

@ -16,15 +16,28 @@
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
#define S3C2410_GPIO_BANKB (32*1)
#define S3C2410_GPIO_BANKC (32*2)
#define S3C2410_GPIO_BANKD (32*3)
#define S3C2410_GPIO_BANKE (32*4)
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
/* GPIO sizes for various SoCs:
*
* 2442
* 2410 2412 2440 2443 2416
* ---- ---- ---- ---- ----
* A 23 22 25 16 25
* B 11 11 11 11 9
* C 16 15 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 9 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 7
* M -- -- -- 2 2
*/
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)

4
arch/arm/mach-s3c2410/include/mach/gpio-track.h
View File

@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG(10))
if (pin > S3C_GPIO_END)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL;
return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */

8
arch/arm/mach-s3c2410/include/mach/gpio.h
View File

@ -20,10 +20,18 @@
* devices that need GPIO.
*/
#ifdef CONFIG_CPU_S3C244X
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
#else
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#endif
#include <asm-generic/gpio.h>
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
#ifdef CONFIG_CPU_S3C24XX
#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
#else
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
#endif

3
arch/arm/mach-s3c2410/include/mach/irqs.h
View File

@ -187,6 +187,9 @@
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
#ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#else

3
arch/arm/mach-s3c2410/include/mach/map.h
View File

@ -67,6 +67,8 @@
#define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2416_PA_HSMMC0 (0x4AC00000)
#define S3C2443_PA_FB (0x4C800000)
/* S3C2412 memory and IO controls */
#define S3C2412_PA_SSMC (0x4F000000)
#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
@ -106,6 +108,7 @@
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND
#define S3C_PA_FB S3C2443_PA_FB
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST

22
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View File

@ -17,29 +17,11 @@
#include <mach/gpio-nrs.h>
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
#define S3C24XX_MISCCR S3C2400_MISCCR
#define S3C24XX_MISCCR S3C2400_MISCCR
#else
#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#endif /* CONFIG_CPU_S3C2400 */
/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
(2 * (S3C2400_BANKNUM(pin)-2)))
#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)

3
arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
View File

@ -83,8 +83,7 @@
#define S3C2443_HCLKCON_DMA4 (1<<4)
#define S3C2443_HCLKCON_DMA5 (1<<5)
#define S3C2443_HCLKCON_CAMIF (1<<8)
#define S3C2443_HCLKCON_DISP (1<<9)
#define S3C2443_HCLKCON_LCDC (1<<10)
#define S3C2443_HCLKCON_LCDC (1<<9)
#define S3C2443_HCLKCON_USBH (1<<11)
#define S3C2443_HCLKCON_USBD (1<<12)
#define S3C2443_HCLKCON_HSMMC (1<<16)

2
arch/arm/mach-s3c2410/mach-bast.c
View File

@ -633,7 +633,7 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
s3c_hwmon_set_platdata(&bast_hwmon_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);

12
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -46,7 +46,6 @@
#include <mach/h1940.h>
#include <mach/h1940-latch.h>
#include <mach/fb.h>
#include <mach/ts.h>
#include <plat/udc.h>
#include <plat/iic.h>
@ -57,6 +56,7 @@
#include <plat/pll.h>
#include <plat/pm.h>
#include <plat/mci.h>
#include <plat/ts.h>
static struct map_desc h1940_iodesc[] __initdata = {
[0] = {
@ -146,6 +146,7 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
.delay = 10000,
.presc = 49,
.oversampling_shift = 2,
.cfg_gpio = s3c24xx_ts_cfg_gpio,
};
/**
@ -163,8 +164,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
.xres = 240,
.yres = 320,
.bpp = 16,
.left_margin = 20,
.right_margin = 8,
.left_margin = 8,
.right_margin = 20,
.hsync_len = 4,
.upper_margin = 8,
.lower_margin = 7,
@ -272,7 +273,6 @@ static struct platform_device h1940_lcd_powerdev = {
};
static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_ts,
&s3c_device_ohci,
&s3c_device_lcd,
&s3c_device_wdt,
@ -286,6 +286,8 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_timer[0],
&h1940_backlight,
&h1940_lcd_powerdev,
&s3c_device_adc,
&s3c_device_ts,
};
static void __init h1940_map_io(void)
@ -339,7 +341,7 @@ static void __init h1940_init(void)
}
MACHINE_START(H1940, "IPAQ-H1940")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

76
arch/arm/mach-s3c2410/mach-n30.c
View File

@ -26,6 +26,7 @@
#include <linux/serial_core.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/mmc/host.h>
#include <mach/hardware.h>
#include <asm/irq.h>
@ -46,6 +47,7 @@
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/mci.h>
#include <plat/s3c2410.h>
#include <plat/udc.h>
@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = {
{
.gpio = S3C2410_GPF(0),
.code = KEY_POWER,
.type = EV_PWR,
.desc = "Power",
.active_low = 0,
.wakeup = 1,
},
{
.gpio = S3C2410_GPG(9),
@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
.def_trigger = "",
};
/* This is the blue LED on the device. Originaly used to indicate GPS activity
* by flashing. */
static struct s3c24xx_led_platdata n35_blue_led_pdata = {
.name = "blue_led",
.gpio = S3C2410_GPD(8),
.def_trigger = "",
};
/* This LED is driven by the battery microcontroller, and is blinking
* red, blinking green or solid green when the battery is low,
* charging or full respectively. By driving GPD9 low, it's possible
@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = {
.def_trigger = "",
};
static struct s3c24xx_led_platdata n35_warning_led_pdata = {
.name = "warning_led",
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.gpio = S3C2410_GPD(9),
.def_trigger = "",
};
static struct platform_device n30_blue_led = {
.name = "s3c24xx_led",
.id = 1,
@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = {
},
};
static struct platform_device n35_blue_led = {
.name = "s3c24xx_led",
.id = 1,
.dev = {
.platform_data = &n35_blue_led_pdata,
},
};
static struct platform_device n30_warning_led = {
.name = "s3c24xx_led",
.id = 2,
@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = {
},
};
static struct platform_device n35_warning_led = {
.name = "s3c24xx_led",
.id = 2,
.dev = {
.platform_data = &n35_warning_led_pdata,
},
};
static struct s3c2410fb_display n30_display __initdata = {
.type = S3C2410_LCDCON1_TFT,
.width = 240,
@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
.lpcsel = 0x06,
};
static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
{
switch (power_mode) {
case MMC_POWER_ON:
case MMC_POWER_UP:
gpio_set_value(S3C2410_GPG(4), 1);
break;
case MMC_POWER_OFF:
default:
gpio_set_value(S3C2410_GPG(4), 0);
break;
}
}
static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
.gpio_detect = S3C2410_GPF(1),
.gpio_wprotect = S3C2410_GPG(10),
.ocr_avail = MMC_VDD_32_33,
.set_power = n30_sdi_set_power,
};
static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_ohci,
&s3c_device_rtc,
&s3c_device_usbgadget,
&s3c_device_sdi,
&n30_button_device,
&n30_blue_led,
&n30_warning_led,
@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_usbgadget,
&s3c_device_sdi,
&n35_button_device,
&n35_blue_led,
&n35_warning_led,
};
static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
@ -490,17 +552,15 @@ static void __init n30_map_io(void)
s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
}
static void __init n30_init_irq(void)
{
s3c24xx_init_irq();
}
/* GPB3 is the line that controls the pull-up for the USB D+ line */
static void __init n30_init(void)
{
WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
s3c24xx_fb_set_platdata(&n30_fb_info);
s3c24xx_udc_set_platdata(&n30_udc_cfg);
s3c24xx_mci_set_platdata(&n30_mci_cfg);
s3c_i2c0_set_platdata(&n30_i2ccfg);
/* Turn off suspend on both USB ports, and switch the
@ -532,7 +592,7 @@ static void __init n30_init(void)
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1,
S3C2410_MISCCR_USBSUSPND1);
S3C2410_MISCCR_USBSUSPND0);
platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
}
@ -550,7 +610,7 @@ MACHINE_START(N30, "Acer-N30")
.boot_params = S3C2410_SDRAM_PA + 0x100,
.timer = &s3c24xx_timer,
.init_machine = n30_init,
.init_irq = n30_init_irq,
.init_irq = s3c24xx_init_irq,
.map_io = n30_map_io,
MACHINE_END
@ -562,6 +622,6 @@ MACHINE_START(N35, "Acer-N35")
.boot_params = S3C2410_SDRAM_PA + 0x100,
.timer = &s3c24xx_timer,
.init_machine = n30_init,
.init_irq = n30_init_irq,
.init_irq = s3c24xx_init_irq,
.map_io = n30_map_io,
MACHINE_END

15
arch/arm/mach-s3c2410/pm.c
View File

@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void)
__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
}
/* the RX3715 uses similar code and the same H1940 and the
/* RX3715 and RX1950 use similar to H1940 code and the
* same offsets for resume and checksum pointers */
if (machine_is_rx3715()) {
if (machine_is_rx3715() || machine_is_rx1950()) {
void *base = phys_to_virt(H1940_SUSPEND_CHECK);
unsigned long ptr;
unsigned long calc = 0;
@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void)
if ( machine_is_aml_m5900() )
s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
if (machine_is_rx1950()) {
/* According to S3C2442 user's manual, page 7-17,
* when the system is operating in NAND boot mode,
* the hardware pin configuration - EINT[23:21] –
* must be set as input for starting up after
* wakeup from sleep mode
*/
s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
}
}
static int s3c2410_pm_resume(struct sys_device *dev)

20
arch/arm/mach-s3c2412/gpio.c
View File

@ -16,41 +16,43 @@
#include <linux/types.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <plat/gpio-core.h>
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long offs = pin - chip->chip.base;
unsigned long flags;
unsigned long slpcon;
offs *= 2;
if (pin < S3C2410_GPIO_BANKB)
if (pin < S3C2410_GPB(0))
return -EINVAL;
if (pin >= S3C2410_GPIO_BANKF &&
pin <= S3C2410_GPIO_BANKG)
if (pin >= S3C2410_GPF(0) &&
pin <= S3C2410_GPG(16))
return -EINVAL;
if (pin > (S3C2410_GPIO_BANKH + 32))
if (pin > S3C2410_GPH(16))
return -EINVAL;
local_irq_save(flags);
slpcon = __raw_readl(base + 0x0C);
slpcon = __raw_readl(chip->base + 0x0C);
slpcon &= ~(3 << offs);
slpcon |= state << offs;
__raw_writel(slpcon, base + 0x0C);
__raw_writel(slpcon, chip->base + 0x0C);
local_irq_restore(flags);

2
arch/arm/mach-s3c2412/mach-jive.c
View File

@ -674,7 +674,7 @@ static void __init jive_machine_init(void)
}
MACHINE_START(JIVE, "JIVE")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

6
arch/arm/mach-s3c2412/mach-smdk2413.c
View File

@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void)
}
MACHINE_START(S3C2413, "S3C2413")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,
@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413")
MACHINE_END
MACHINE_START(SMDK2412, "SMDK2412")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,
@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
MACHINE_END
MACHINE_START(SMDK2413, "SMDK2413")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

1
arch/arm/mach-s3c2416/Kconfig
View File

@ -30,6 +30,7 @@ menu "S3C2416 Machines"
config MACH_SMDK2416
bool "SMDK2416"
select CPU_S3C2416
select S3C_DEV_FB
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
help

62
arch/arm/mach-s3c2416/mach-smdk2416.c
View File

@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/fb.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -36,16 +37,19 @@
#include <mach/regs-lcd.h>
#include <mach/idle.h>
#include <mach/fb.h>
#include <mach/leds-gpio.h>
#include <plat/iic.h>
#include <plat/s3c2416.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/nand.h>
#include <plat/regs-fb-v4.h>
#include <plat/fb.h>
#include <plat/common-smdk.h>
static struct map_desc smdk2416_iodesc[] __initdata = {
@ -109,7 +113,54 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
}
};
struct s3c_fb_pd_win smdk2416_fb_win[] = {
[0] = {
/* think this is the same as the smdk6410 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.default_bpp = 16,
.max_bpp = 32,
},
};
static void s3c2416_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
static struct s3c_fb_platdata smdk2416_fb_platdata = {
.win[0] = &smdk2416_fb_win[0],
.setup_gpio = s3c2416_fb_gpio_setup_24bpp,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct platform_device *smdk2416_devices[] __initdata = {
&s3c_device_fb,
&s3c_device_wdt,
&s3c_device_ohci,
&s3c_device_i2c0,
@ -119,20 +170,25 @@ static struct platform_device *smdk2416_devices[] __initdata = {
static void __init smdk2416_map_io(void)
{
s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
}
static void __init smdk2416_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&smdk2416_fb_platdata);
gpio_request(S3C2410_GPB(4), "USBHost Power");
gpio_direction_output(S3C2410_GPB(4), 1);
gpio_request(S3C2410_GPB(3), "Display Power");
gpio_direction_output(S3C2410_GPB(3), 1);
gpio_request(S3C2410_GPB(1), "Display Reset");
gpio_direction_output(S3C2410_GPB(1), 1);
platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
smdk_machine_init();
}

2
arch/arm/mach-s3c2416/s3c2416.c
View File

@ -90,6 +90,8 @@ int __init s3c2416_init(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_device_fb.name = "s3c2443-fb";
return sysdev_register(&s3c2416_sysdev);
}

13
arch/arm/mach-s3c2440/Kconfig
View File

@ -188,4 +188,17 @@ config MACH_MINI2440
Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
available via various sources. It can come with a 3.5" or 7" touch LCD.
config MACH_RX1950
bool "HP iPAQ rx1950"
select CPU_S3C2442
select S3C24XX_DCLK
select PM_H1940 if PM
select I2C
select S3C2410_PWM
select S3C_DEV_NAND
select S3C2410_IOTIMING if S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
help
Say Y here if you're using HP iPAQ rx1950
endmenu

1
arch/arm/mach-s3c2440/Makefile
View File

@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
# extra machine support

582
arch/arm/mach-s3c2440/mach-rx1950.c Normal file
View File

@ -0,0 +1,582 @@
/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
*
* Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
* Copyright (c) 2007-2010 Vasily Khoruzhick
*
* based on smdk2440 written by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/sysdev.h>
#include <linux/pwm_backlight.h>
#include <linux/pwm.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mmc/host.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach-types.h>
#include <mach/regs-gpio.h>
#include <mach/regs-gpioj.h>
#include <mach/h1940.h>
#include <mach/fb.h>
#include <plat/clock.h>
#include <plat/regs-serial.h>
#include <plat/regs-iic.h>
#include <plat/mci.h>
#include <plat/udc.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/irq.h>
#include <plat/ts.h>
#define LCD_PWM_PERIOD 192960
#define LCD_PWM_DUTY 127353
static struct map_desc rx1950_iodesc[] __initdata = {
};
static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
[0] = {
.name = "fclk",
.divisor = 0x0a,
.min_baud = 0,
.max_baud = 0,
},
};
static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
.clocks = rx1950_serial_clocks,
.clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x03,
.ufcon = 0x51,
.clocks = rx1950_serial_clocks,
.clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
},
/* IR port */
[2] = {
.hwport = 2,
.flags = 0,
.ucon = 0x3c5,
.ulcon = 0x43,
.ufcon = 0xf1,
.clocks = rx1950_serial_clocks,
.clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
},
};
static struct s3c2410fb_display rx1950_display = {
.type = S3C2410_LCDCON1_TFT,
.width = 240,
.height = 320,
.xres = 240,
.yres = 320,
.bpp = 16,
.pixclock = 260000,
.left_margin = 10,
.right_margin = 20,
.hsync_len = 10,
.upper_margin = 2,
.lower_margin = 2,
.vsync_len = 2,
.lcdcon5 = S3C2410_LCDCON5_FRM565 |
S3C2410_LCDCON5_INVVCLK |
S3C2410_LCDCON5_INVVLINE |
S3C2410_LCDCON5_INVVFRAME |
S3C2410_LCDCON5_HWSWP |
(0x02 << 13) |
(0x02 << 15),
};
static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
.displays = &rx1950_display,
.num_displays = 1,
.default_display = 0,
.lpcsel = 0x02,
.gpccon = 0xaa9556a9,
.gpccon_mask = 0xffc003fc,
.gpcup = 0x0000ffff,
.gpcup_mask = 0xffffffff,
.gpdcon = 0xaa90aaa1,
.gpdcon_mask = 0xffc0fff0,
.gpdup = 0x0000fcfd,
.gpdup_mask = 0xffffffff,
};
static struct pwm_device *lcd_pwm;
void rx1950_lcd_power(int enable)
{
int i;
static int enabled;
if (enabled == enable)
return;
if (!enable) {
/* GPC11-GPC15->OUTPUT */
for (i = 11; i < 16; i++)
gpio_direction_output(S3C2410_GPC(i), 1);
/* Wait a bit here... */
mdelay(100);
/* GPD2-GPD7->OUTPUT */
/* GPD11-GPD15->OUTPUT */
/* GPD2-GPD7->1, GPD11-GPD15->1 */
for (i = 2; i < 8; i++)
gpio_direction_output(S3C2410_GPD(i), 1);
for (i = 11; i < 16; i++)
gpio_direction_output(S3C2410_GPD(i), 1);
/* Wait a bit here...*/
mdelay(100);
/* GPB0->OUTPUT, GPB0->0 */
gpio_direction_output(S3C2410_GPB(0), 0);
/* GPC1-GPC4->OUTPUT, GPC1-4->0 */
for (i = 1; i < 5; i++)
gpio_direction_output(S3C2410_GPC(i), 0);
/* GPC15-GPC11->0 */
for (i = 11; i < 16; i++)
gpio_direction_output(S3C2410_GPC(i), 0);
/* GPD15-GPD11->0, GPD2->GPD7->0 */
for (i = 11; i < 16; i++)
gpio_direction_output(S3C2410_GPD(i), 0);
for (i = 2; i < 8; i++)
gpio_direction_output(S3C2410_GPD(i), 0);
/* GPC6->0, GPC7->0, GPC5->0 */
gpio_direction_output(S3C2410_GPC(6), 0);
gpio_direction_output(S3C2410_GPC(7), 0);
gpio_direction_output(S3C2410_GPC(5), 0);
/* GPB1->OUTPUT, GPB1->0 */
gpio_direction_output(S3C2410_GPB(1), 0);
pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
pwm_disable(lcd_pwm);
/* GPC0->0, GPC10->0 */
gpio_direction_output(S3C2410_GPC(0), 0);
gpio_direction_output(S3C2410_GPC(10), 0);
} else {
pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD);
pwm_enable(lcd_pwm);
gpio_direction_output(S3C2410_GPC(0), 1);
gpio_direction_output(S3C2410_GPC(5), 1);
s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1);
gpio_direction_output(S3C2410_GPC(7), 1);
for (i = 1; i < 5; i++)
s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
for (i = 11; i < 16; i++)
s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
for (i = 2; i < 8; i++)
s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
for (i = 11; i < 16; i++)
s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
gpio_direction_output(S3C2410_GPC(10), 1);
gpio_direction_output(S3C2410_GPC(6), 1);
}
enabled = enable;
}
static void rx1950_bl_power(int enable)
{
static int enabled;
if (enabled == enable)
return;
if (!enable) {
gpio_direction_output(S3C2410_GPB(0), 0);
} else {
/* LED driver need a "push" to power on */
gpio_direction_output(S3C2410_GPB(0), 1);
/* Warm up backlight for one period of PWM.
* Without this trick its almost impossible to
* enable backlight with low brightness value
*/
ndelay(48000);
s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
}
enabled = enable;
}
static int rx1950_backlight_init(struct device *dev)
{
WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight"));
lcd_pwm = pwm_request(1, "RX1950 LCD");
if (IS_ERR(lcd_pwm)) {
dev_err(dev, "Unable to request PWM for LCD power!\n");
return PTR_ERR(lcd_pwm);
}
rx1950_lcd_power(1);
rx1950_bl_power(1);
return 0;
}
static void rx1950_backlight_exit(struct device *dev)
{
rx1950_bl_power(0);
rx1950_lcd_power(0);
pwm_free(lcd_pwm);
gpio_free(S3C2410_GPB(0));
}
static int rx1950_backlight_notify(struct device *dev, int brightness)
{
if (!brightness) {
rx1950_bl_power(0);
rx1950_lcd_power(0);
} else {
rx1950_lcd_power(1);
rx1950_bl_power(1);
}
return brightness;
}
static struct platform_pwm_backlight_data rx1950_backlight_data = {
.pwm_id = 0,
.max_brightness = 24,
.dft_brightness = 4,
.pwm_period_ns = 48000,
.init = rx1950_backlight_init,
.notify = rx1950_backlight_notify,
.exit = rx1950_backlight_exit,
};
static struct platform_device rx1950_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[0].dev,
.platform_data = &rx1950_backlight_data,
},
};
static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
{
switch (power_mode) {
case MMC_POWER_OFF:
gpio_direction_output(S3C2410_GPJ(1), 0);
break;
case MMC_POWER_UP:
case MMC_POWER_ON:
gpio_direction_output(S3C2410_GPJ(1), 1);
break;
default:
break;
}
}
static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = {
.gpio_detect = S3C2410_GPF(5),
.gpio_wprotect = S3C2410_GPH(8),
.set_power = rx1950_set_mmc_power,
.ocr_avail = MMC_VDD_32_33,
};
static struct mtd_partition rx1950_nand_part[] = {
[0] = {
.name = "Boot0",
.offset = 0,
.size = 0x4000,
.mask_flags = MTD_WRITEABLE,
},
[1] = {
.name = "Boot1",
.offset = MTDPART_OFS_APPEND,
.size = 0x40000,
.mask_flags = MTD_WRITEABLE,
},
[2] = {
.name = "Kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0x300000,
.mask_flags = 0,
},
[3] = {
.name = "Filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0,
},
};
static struct s3c2410_nand_set rx1950_nand_sets[] = {
[0] = {
.name = "Internal",
.nr_chips = 1,
.nr_partitions = ARRAY_SIZE(rx1950_nand_part),
.partitions = rx1950_nand_part,
},
};
static struct s3c2410_platform_nand rx1950_nand_info = {
.tacls = 25,
.twrph0 = 50,
.twrph1 = 15,
.nr_sets = ARRAY_SIZE(rx1950_nand_sets),
.sets = rx1950_nand_sets,
};
static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd)
{
switch (cmd) {
case S3C2410_UDC_P_ENABLE:
gpio_direction_output(S3C2410_GPJ(5), 1);
break;
case S3C2410_UDC_P_DISABLE:
gpio_direction_output(S3C2410_GPJ(5), 0);
break;
case S3C2410_UDC_P_RESET:
break;
default:
break;
}
}
static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
.udc_command = rx1950_udc_pullup,
.vbus_pin = S3C2410_GPG(5),
.vbus_pin_inverted = 1,
};
static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = {
.delay = 10000,
.presc = 49,
.oversampling_shift = 3,
};
static struct gpio_keys_button rx1950_gpio_keys_table[] = {
{
.code = KEY_POWER,
.gpio = S3C2410_GPF(0),
.active_low = 1,
.desc = "Power button",
.wakeup = 1,
},
{
.code = KEY_F5,
.gpio = S3C2410_GPF(7),
.active_low = 1,
.desc = "Record button",
},
{
.code = KEY_F1,
.gpio = S3C2410_GPG(0),
.active_low = 1,
.desc = "Calendar button",
},
{
.code = KEY_F2,
.gpio = S3C2410_GPG(2),
.active_low = 1,
.desc = "Contacts button",
},
{
.code = KEY_F3,
.gpio = S3C2410_GPG(3),
.active_low = 1,
.desc = "Mail button",
},
{
.code = KEY_F4,
.gpio = S3C2410_GPG(7),
.active_low = 1,
.desc = "WLAN button",
},
{
.code = KEY_LEFT,
.gpio = S3C2410_GPG(10),
.active_low = 1,
.desc = "Left button",
},
{
.code = KEY_RIGHT,
.gpio = S3C2410_GPG(11),
.active_low = 1,
.desc = "Right button",
},
{
.code = KEY_UP,
.gpio = S3C2410_GPG(4),
.active_low = 1,
.desc = "Up button",
},
{
.code = KEY_DOWN,
.gpio = S3C2410_GPG(6),
.active_low = 1,
.desc = "Down button",
},
{
.code = KEY_ENTER,
.gpio = S3C2410_GPG(9),
.active_low = 1,
.desc = "Ok button"
},
};
static struct gpio_keys_platform_data rx1950_gpio_keys_data = {
.buttons = rx1950_gpio_keys_table,
.nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table),
};
static struct platform_device rx1950_device_gpiokeys = {
.name = "gpio-keys",
.dev.platform_data = &rx1950_gpio_keys_data,
};
static struct s3c2410_platform_i2c rx1950_i2c_data = {
.flags = 0,
.slave_addr = 0x42,
.frequency = 400 * 1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
static struct platform_device *rx1950_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_sdi,
&s3c_device_adc,
&s3c_device_ts,
&s3c_device_timer[0],
&s3c_device_timer[1],
&rx1950_backlight,
&rx1950_device_gpiokeys,
};
static struct clk *rx1950_clocks[] __initdata = {
&s3c24xx_clkout0,
&s3c24xx_clkout1,
};
static void __init rx1950_map_io(void)
{
s3c24xx_clkout0.parent = &clk_h;
s3c24xx_clkout1.parent = &clk_f;
s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
s3c24xx_init_clocks(16934000);
s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
/* setup PM */
#ifdef CONFIG_PM_H1940
memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8);
#endif
s3c_pm_init();
}
static void __init rx1950_init_machine(void)
{
int i;
s3c24xx_fb_set_platdata(&rx1950_lcd_cfg);
s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
s3c_i2c0_set_platdata(&rx1950_i2c_data);
s3c_nand_set_platdata(&rx1950_nand_info);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, 0x0);
WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup"));
gpio_direction_output(S3C2410_GPJ(5), 0);
/* mmc power is disabled by default */
WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power"));
gpio_direction_output(S3C2410_GPJ(1), 0);
for (i = 0; i < 8; i++)
WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
for (i = 10; i < 16; i++)
WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
for (i = 2; i < 8; i++)
WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
for (i = 11; i < 16; i++)
WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
}
MACHINE_START(RX1950, "HP iPAQ RX1950")
/* Maintainers: Vasily Khoruzhick */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,
.map_io = rx1950_map_io,
.init_irq = s3c24xx_init_irq,
.init_machine = rx1950_init_machine,
.timer = &s3c24xx_timer,
MACHINE_END

2
arch/arm/mach-s3c2440/mach-rx3715.c
View File

@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void)
}
MACHINE_START(RX3715, "IPAQ-RX3715")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

2
arch/arm/mach-s3c2440/mach-smdk2440.c
View File

@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void)
}
MACHINE_START(S3C2440, "SMDK2440")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

2
arch/arm/mach-s3c2443/mach-smdk2443.c
View File

@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void)
}
MACHINE_START(SMDK2443, "SMDK2443")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100,

1
arch/arm/mach-s3c64xx/Kconfig
View File

@ -85,6 +85,7 @@ config MACH_ANW6410
config MACH_SMDK6410
bool "SMDK6410"
select CPU_S3C6410
select SAMSUNG_DEV_ADC
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1

3
arch/arm/mach-s3c64xx/Makefile
View File

@ -56,7 +56,6 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
# device support
obj-y += dev-uart.o
obj-y += dev-rtc.o
obj-y += dev-audio.o
obj-$(CONFIG_S3C_ADC) += dev-adc.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o

36
arch/arm/mach-s3c64xx/clock.c
View File

@ -88,6 +88,12 @@ struct clk clk_48m = {
.enable = clk_48m_ctrl,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
.id = -1,
.rate = 48000000,
};
static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk,
int enable)
@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = {
.id = -1,
};
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
.id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
.id = -1,
@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = {
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
static struct clk *clkset_audio2_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iisv4_cd,
[4] = &clk_pcm_cd,
};
static struct clksrc_sources clkset_audio2 = {
.sources = clkset_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_audio2_list),
};
static struct clk *clkset_camif_list[] = {
&clk_h2,
};
@ -650,6 +674,16 @@ static struct clksrc_clk clksrcs[] = {
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1,
}, {
.clk = {
.name = "audio-bus",
.id = -1, /* There's only one IISv4 port */
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
.sources = &clkset_audio2,
}, {
.clk = {
.name = "irda-bus",
@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = {
&clk_ext_xtal_mux,
&clk_iis_cd0,
&clk_iis_cd1,
&clk_iisv4_cd,
&clk_pcm_cd,
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = {
&clk_27m,
&clk_48m,
&clk_h2,
&clk_xusbxti,
};
/**

2
arch/arm/mach-s3c64xx/dma.c
View File

@ -414,7 +414,7 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id,
EXPORT_SYMBOL(s3c2410_dma_enqueue);
int s3c2410_dma_devconfig(int channel,
int s3c2410_dma_devconfig(unsigned int channel,
enum s3c2410_dmasrc source,
unsigned long devaddr)
{

3
arch/arm/mach-s3c64xx/include/mach/map.h
View File

@ -103,5 +103,8 @@
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
#define S3C_PA_RTC S3C64XX_PA_RTC
#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
#endif /* __ASM_ARCH_6400_MAP_H */

1
arch/arm/mach-s3c64xx/include/mach/regs-clock.h
View File

@ -33,6 +33,7 @@
#define S3C_PCLK_GATE S3C_CLKREG(0x34)
#define S3C_SCLK_GATE S3C_CLKREG(0x38)
#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
/* CLKDIV0 */
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)

2
arch/arm/mach-s3c64xx/mach-smdk6400.c
View File

@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void)
}
MACHINE_START(SMDK6400, "SMDK6400")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,

2
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void)
}
MACHINE_START(SMDK6410, "SMDK6410")
/* Maintainer: Ben Dooks <ben@fluff.org> */
/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100,

2
arch/arm/mach-s3c64xx/s3c6410.c
View File

@ -38,6 +38,7 @@
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/adc.h>
#include <mach/s3c6400.h>
#include <mach/s3c6410.h>
@ -52,6 +53,7 @@ void __init s3c6410_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_device_adc.name = "s3c64xx-adc";
s3c_device_nand.name = "s3c6400-nand";
}

1
arch/arm/mach-s5p6440/Kconfig
View File

@ -9,6 +9,7 @@ if ARCH_S5P6440
config CPU_S5P6440
bool
select S3C_PL330_DMA
help
Enable S5P6440 CPU support

6
arch/arm/mach-s5p6440/Makefile
View File

@ -12,8 +12,12 @@ obj- :=
# Core support for S5P6440 system
obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o
obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
# device support
obj-y += dev-audio.o

356
arch/arm/mach-s5p6440/clock.c
View File

@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
};
static struct clk clk_h_low = {
.name = "hclk_low",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
static struct clk clk_p_low = {
.name = "pclk_low",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
enum perf_level {
L0 = 532*1000,
L1 = 266*1000,
@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
.round_rate = s5p6440_armclk_round_rate,
};
static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK)
rate /= 2;
return rate;
}
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
.ops = &(struct clk_ops) {
.get_rate = s5p6440_clk_doutmpll_get_rate,
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
.id = 1,
.parent = &clk_mout_apll.clk,
.ops = &s5p6440_clkarm_ops,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
};
static struct clksrc_clk clk_dout_mpll = {
.clk = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
};
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
.id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clk *clkset_hclklow_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_hclklow = {
.sources = clkset_hclklow_list,
.nr_sources = ARRAY_SIZE(clkset_hclklow_list),
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "hclk_low",
.id = -1,
},
.sources = &clkset_hclklow,
.reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
};
int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
}
static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
}
static int s5p6440_mem_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
{
.name = "nand",
.id = -1,
.parent = &clk_h,
.parent = &clk_hclk.clk,
.enable = s5p6440_mem_ctrl,
.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
}, {
.name = "adc",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIC0,
}, {
.name = "i2s_v40",
.id = 0,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIS2,
}, {
.name = "spi",
.id = 0,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.id = 1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI1,
}, {
@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
}, {
.name = "otg",
.id = -1,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_USB
}, {
.name = "post",
.id = -1,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_POST0
}, {
.name = "lcd",
.id = -1,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_h_low,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
}, {
.name = "rtc",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_RTC,
}, {
.name = "watchdog",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_WDT,
}, {
.name = "timers",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_PWM,
}
}, {
.name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "etm",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irom",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "2d",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 8),
},
};
/*
@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
{
.name = "gpio",
.id = -1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_GPIO,
}, {
.name = "uart",
.id = 0,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.id = 1,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.id = 2,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.id = 3,
.parent = &clk_p_low,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART3,
}
}, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 1),
},
};
static struct clk clk_iis_cd_v40 = {
@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
.id = -1,
};
static struct clk *clkset_spi_mmc_list[] = {
static struct clk *clkset_group1_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_dout_mpll.clk,
&clk_fin_epll,
};
static struct clksrc_sources clkset_spi_mmc = {
.sources = clkset_spi_mmc_list,
.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
static struct clksrc_sources clkset_group1 = {
.sources = clkset_group1_list,
.nr_sources = ARRAY_SIZE(clkset_group1_list),
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll
&clk_dout_mpll.clk,
};
static struct clksrc_sources clkset_uart = {
@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_audio_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
static struct clksrc_sources clkset_audio = {
.sources = clkset_audio_list,
.nr_sources = ARRAY_SIZE(clkset_audio_list),
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC0,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_spi_mmc,
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
}, {
@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC1,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_spi_mmc,
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
}, {
@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC2,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_spi_mmc,
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
}, {
@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_SPI0,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_spi_mmc,
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
}, {
@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_SPI1,
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_spi_mmc,
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
}
}, {
.clk = {
.name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
},
};
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
&clk_dout_mpll,
&clk_armclk,
&clk_hclk,
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
};
void __init_or_cpufreq s5p6440_setup_clocks(void)
@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
u32 clkdiv0;
u32 clkdiv3;
/* Set S5P6440 functions for clk_fout_epll */
clk_fout_epll.enable = s5p6440_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
/* Set S5P6440 functions for arm clock */
clk_arm.parent = &clk_mout_apll.clk;
clk_arm.ops = &s5p6440_clkarm_ops;
clk_48m.enable = s5p6440_clk48m_ctrl;
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
clkdiv3 = __raw_readl(S5P_CLK_DIV3);
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM);
hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
/* Asynchronous mode */
hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
} else {
/* Synchronous mode */
hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
}
pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_h_low.rate = hclk_low;
clk_p_low.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_iis_cd_v40,
&clk_pcm_cd,
&clk_p_low,
&clk_h_low,
};
void __init s5p6440_register_clocks(void)
@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));

2
arch/arm/mach-s5p6440/cpu.c
View File

@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
static struct sysdev_class s5p6440_sysclass = {
struct sysdev_class s5p6440_sysclass = {
.name = "s5p6440-core",
};

127
arch/arm/mach-s5p6440/dev-audio.c Normal file
View File

@ -0,0 +1,127 @@
/* linux/arch/arm/mach-s5p6440/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/gpio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6440_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5p6440_cfg_i2s,
};
static struct resource s5p6440_iis0_resource[] = {
[0] = {
.start = S5P6440_PA_I2S,
.end = S5P6440_PA_I2S + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_iis = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
.resource = s5p6440_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6440_pcm_cfg_gpio,
};
static struct resource s5p6440_pcm0_resource[] = {
[0] = {
.start = S5P6440_PA_PCM,
.end = S5P6440_PA_PCM + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_pcm = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
.resource = s5p6440_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};

105
arch/arm/mach-s5p6440/dma.c Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6440_pdma_resource[] = {
[0] = {
.start = S5P6440_PA_PDMA,
.end = S5P6440_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DMA0,
.end = IRQ_DMA0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_MAX,
[10] = DMACH_PCM0_TX,
[11] = DMACH_PCM0_RX,
[12] = DMACH_I2S0_TX,
[13] = DMACH_I2S0_RX,
[14] = DMACH_SPI0_TX,
[15] = DMACH_SPI0_RX,
[16] = DMACH_MAX,
[17] = DMACH_MAX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_SPI1_TX,
[21] = DMACH_SPI1_RX,
[22] = DMACH_MAX,
[23] = DMACH_MAX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MAX,
[28] = DMACH_MAX,
[29] = DMACH_PWM,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6440_device_pdma = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6440_pdma_resource),
.resource = s5p6440_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6440_pdma_pdata,
},
};
static struct platform_device *s5p6440_dmacs[] __initdata = {
&s5p6440_device_pdma,
};
static int __init s5p6440_dma_init(void)
{
platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
return 0;
}
arch_initcall(s5p6440_dma_init);

26
arch/arm/mach-s5p6440/include/mach/dma.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */

8
arch/arm/mach-s5p6440/include/mach/map.h
View File

@ -29,6 +29,8 @@
#define S5P6440_PA_VIC0 (0xE4000000)
#define S5P_PA_VIC0 S5P6440_PA_VIC0
#define S5P6440_PA_PDMA 0xE9000000
#define S5P6440_PA_VIC1 (0xE4100000)
#define S5P_PA_VIC1 S5P6440_PA_VIC1
@ -61,6 +63,12 @@
#define S5P6440_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6440_PA_SDRAM
/* I2S */
#define S5P6440_PA_I2S 0xF2000000
/* PCM */
#define S5P6440_PA_PCM 0xF2100000
/* compatibiltiy defines. */
#define S3C_PA_UART S5P6440_PA_UART
#define S3C_PA_IIC S5P6440_PA_IIC0

24
arch/arm/mach-s5p6440/include/mach/pwm-clock.h
View File

@ -1,11 +1,14 @@
/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Copyright 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5P6440 - pwm clock and timer support
*
@ -14,16 +17,19 @@
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0.
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C2410_TCFG1_MUX_TCLK;
return 0;
}
/**
@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
return 1 << tcfg1;
}
/**
@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 0;
return 1;
}
/**
@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div) - 1;
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
#define S3C_TCFG1_MUX_TCLK 0
#endif /* __ASM_ARCH_PWMCLK_H */

1
arch/arm/mach-s5p6440/mach-smdk6440.c
View File

@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
};
static struct platform_device *smdk6440_devices[] __initdata = {
&s5p6440_device_iis,
};
static void __init smdk6440_map_io(void)

2
arch/arm/plat-s5p/setup-i2c0.c → arch/arm/mach-s5p6440/setup-i2c0.c
View File

@ -1,4 +1,4 @@
/* linux/arch/arm/plat-s5p/setup-i2c0.c
/* linux/arch/arm/mach-s5p6440/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/

1
arch/arm/mach-s5p6442/Kconfig
View File

@ -12,6 +12,7 @@ if ARCH_S5P6442
config CPU_S5P6442
bool
select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5P6442 CPU support

6
arch/arm/mach-s5p6442/Makefile
View File

@ -12,8 +12,12 @@ obj- :=
# Core support for S5P6442 system
obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o
obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
# device support
obj-y += dev-audio.o

2
arch/arm/mach-s5p6442/cpu.c
View File

@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
static struct sysdev_class s5p6442_sysclass = {
struct sysdev_class s5p6442_sysclass = {
.name = "s5p6442-core",
};

197
arch/arm/mach-s5p6442/dev-audio.c Normal file
View File

@ -0,0 +1,197 @@
/* linux/arch/arm/mach-s5p6442/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/gpio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
break;
case -1:
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
};
static struct resource s5p6442_iis0_resource[] = {
[0] = {
.start = S5P6442_PA_I2S0,
.end = S5P6442_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis0 = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
.resource = s5p6442_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
static struct resource s5p6442_iis1_resource[] = {
[0] = {
.start = S5P6442_PA_I2S1,
.end = S5P6442_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S1_TX,
.end = DMACH_I2S1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S1_RX,
.end = DMACH_I2S1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis1 = {
.name = "s3c64xx-iis",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
.resource = s5p6442_iis1_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6442_pcm_cfg_gpio,
};
static struct resource s5p6442_pcm0_resource[] = {
[0] = {
.start = S5P6442_PA_PCM0,
.end = S5P6442_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
.resource = s5p6442_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5p6442_pcm1_resource[] = {
[0] = {
.start = S5P6442_PA_PCM1,
.end = S5P6442_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM1_TX,
.end = DMACH_PCM1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM1_RX,
.end = DMACH_PCM1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
.resource = s5p6442_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};

105
arch/arm/mach-s5p6442/dma.c Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6442_pdma_resource[] = {
[0] = {
.start = S5P6442_PA_PDMA,
.end = S5P6442_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA,
.end = IRQ_PDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_MAX,
[7] = DMACH_MAX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_PCM0_RX,
[21] = DMACH_PCM0_TX,
[22] = DMACH_PCM1_RX,
[23] = DMACH_PCM1_TX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MSM_REQ0,
[28] = DMACH_MSM_REQ1,
[29] = DMACH_MSM_REQ2,
[30] = DMACH_MSM_REQ3,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6442_device_pdma = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
.resource = s5p6442_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_pdma_pdata,
},
};
static struct platform_device *s5p6442_dmacs[] __initdata = {
&s5p6442_device_pdma,
};
static int __init s5p6442_dma_init(void)
{
platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
return 0;
}
arch_initcall(s5p6442_dma_init);

26
arch/arm/mach-s5p6442/include/mach/dma.h Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */

11
arch/arm/mach-s5p6442/include/mach/map.h
View File

@ -34,6 +34,9 @@
#define S5P6442_PA_VIC2 (0xE4200000)
#define S5P_PA_VIC2 S5P6442_PA_VIC2
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P6442_PA_TIMER
@ -51,6 +54,14 @@
#define S5P6442_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
/* I2S */
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
/* PCM */
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* compatibiltiy defines. */
#define S3C_PA_UART S5P6442_PA_UART
#define S3C_PA_IIC S5P6442_PA_IIC0

21
arch/arm/mach-s5p6442/include/mach/pwm-clock.h
View File

@ -1,13 +1,14 @@
/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Copyright 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5P6442 - pwm clock and timer support
*
@ -21,14 +22,14 @@
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0.
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C2410_TCFG1_MUX_TCLK;
return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
return 1 << tcfg1;
}
/**
@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 0;
return 1;
}
/**
@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div) - 1;
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */

1
arch/arm/mach-s5p6442/mach-smdk6442.c
View File

@ -65,6 +65,7 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
};
static struct platform_device *smdk6442_devices[] __initdata = {
&s5p6442_device_iis0,
};
static void __init smdk6442_map_io(void)

25
arch/arm/mach-s5p6442/setup-i2c0.c Normal file
View File

@ -0,0 +1,25 @@
/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
/* Will be populated later */
}

15
arch/arm/mach-s5pc100/Kconfig
View File

@ -12,12 +12,22 @@ config CPU_S5PC100
help
Enable S5PC100 CPU support
config S5PC100_SETUP_FB_24BPP
bool
help
Common setup code for S5PC1XX with an 24bpp RGB display helper.
config S5PC100_SETUP_SDHCI
bool
select S5PC1XX_SETUP_SDHCI_GPIO
help
Internal helper functions for S5PC100 based SDHCI systems
config S5PC100_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config MACH_SMDKC100
bool "SMDKC100"
select CPU_S5PC100
@ -26,9 +36,8 @@ config MACH_SMDKC100
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S5PC1XX_SETUP_I2C0
select S5PC1XX_SETUP_I2C1
select S5PC1XX_SETUP_FB_24BPP
select S5PC100_SETUP_FB_24BPP
select S5PC100_SETUP_I2C1
select S5PC100_SETUP_SDHCI
help
Machine support for the Samsung SMDKC100

5
arch/arm/mach-s5pc100/Makefile
View File

@ -11,10 +11,13 @@ obj- :=
# Core support for S5PC100 system
obj-$(CONFIG_CPU_S5PC100) += cpu.o
obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o
obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
# Helper and device support
obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
# machine support

1358
arch/arm/mach-s5pc100/clock.c Normal file
View File

File diff suppressed because it is too large Load Diff

107
arch/arm/plat-s5pc1xx/gpiolib.c → arch/arm/mach-s5pc100/gpiolib.c
View File

@ -17,11 +17,11 @@
#include <linux/gpio.h>
#include <mach/map.h>
#include <mach/regs-gpio.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
/* S5PC100 GPIO bank summary:
*
@ -61,74 +61,7 @@
* L3 8 4Bit None
*/
#define OFF_GPCON (0x00)
#define OFF_GPDAT (0x04)
#define con_4bit_shift(__off) ((__off) * 4)
#if 1
#define gpio_dbg(x...) do { } while (0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG x)
#endif
/* The s5pc1xx_gpiolib routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
* the output.
*/
static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + OFF_GPCON);
gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, base + OFF_GPCON);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
#if 0
static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
{
return S3C_IRQ_GPIO(chip->base + offset);
@ -152,7 +85,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
return IRQ_EINT(24 + offset);
return -EINVAL;
}
#endif
static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
@ -452,12 +385,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
extern struct irq_chip s5pc1xx_gpioint;
extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s5pc1xx_gpiolib_input;
chip->chip.direction_output = s5pc1xx_gpiolib_output;
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
#if 0
/* Interrupt */
if (chip->config == &gpio_cfg) {
int i, irq;
@ -473,31 +403,26 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
}
} else if (chip->config == &gpio_cfg_eint)
chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
}
static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
#endif
}
static __init int s5pc1xx_gpiolib_init(void)
{
struct s3c_gpio_chip *chips;
struct s3c_gpio_chip *chip;
int nr_chips;
chips = s5pc100_gpio_chips;
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
chip = s5pc100_gpio_chips;
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
for (; nr_chips > 0; nr_chips--, chip++)
s5pc100_gpiolib_link(chip);
samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
ARRAY_SIZE(s5pc100_gpio_chips));
#if 0
/* Interrupt */
set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
#endif
return 0;
}
core_initcall(s5pc1xx_gpiolib_init);

95
arch/arm/mach-s5pc100/include/mach/gpio.h
View File

@ -12,6 +12,9 @@
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
@ -52,11 +55,6 @@
#define S5PC100_GPIO_L2_NR (8)
#define S5PC100_GPIO_L3_NR (8)
#define S5PC100_GPIO_L4_NR (8)
#define S5PC100_GPIO_MP00_NR (8)
#define S5PC100_GPIO_MP01_NR (8)
#define S5PC100_GPIO_MP02_NR (8)
#define S5PC100_GPIO_MP03_NR (8)
#define S5PC100_GPIO_MP04_NR (5)
/* GPIO bank numbes */
@ -65,50 +63,45 @@
* change from one gpio bank to another can be caught.
*/
#define S5PC1XX_GPIO_NEXT(__gpio) \
#define S5PC100_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
enum s5p_gpio_number {
S5PC100_GPIO_A0_START = 0,
S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
};
/* S5PC100 GPIO number definitions. */
@ -146,17 +139,13 @@ enum s3c_gpio_number {
#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr))
#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr))
#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr))
#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr))
#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr))
#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr))
/* It used the end of the S5PC1XX gpios */
/* It used the end of the S5PC100 gpios */
#define S3C_GPIO_END S5PC100_GPIO_END
/* define the number of gpios we need to the one after the MP04() range */
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

71
arch/arm/mach-s5pc100/include/mach/regs-clock.h Normal file
View File

@ -0,0 +1,71 @@
/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PC100 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
#define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x104)
#define S5P_EPLL_CON S5P_CLKREG(0x108)
#define S5P_HPLL_CON S5P_CLKREG(0x10C)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
#define S5P_CLK_OUT S5P_CLKREG(0x400)
#define S5P_CLKGATE_D00 S5P_CLKREG(0x500)
#define S5P_CLKGATE_D01 S5P_CLKREG(0x504)
#define S5P_CLKGATE_D02 S5P_CLKREG(0x508)
#define S5P_CLKGATE_D10 S5P_CLKREG(0x520)
#define S5P_CLKGATE_D11 S5P_CLKREG(0x524)
#define S5P_CLKGATE_D12 S5P_CLKREG(0x528)
#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C)
#define S5P_CLKGATE_D14 S5P_CLKREG(0x530)
#define S5P_CLKGATE_D15 S5P_CLKREG(0x534)
#define S5P_CLKGATE_D20 S5P_CLKREG(0x540)
#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560)
#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564)
/* CLKDIV0 */
#define S5P_CLKDIV0_D0_MASK (0x7<<8)
#define S5P_CLKDIV0_D0_SHIFT (8)
#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
#define S5P_CLKDIV0_PCLKD0_SHIFT (12)
/* CLKDIV1 */
#define S5P_CLKDIV1_D1_MASK (0x7<<12)
#define S5P_CLKDIV1_D1_SHIFT (12)
#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
#endif /* __ASM_ARCH_REGS_CLOCK_H */

8
arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h → arch/arm/mach-s5pc100/include/mach/regs-gpio.h
View File

@ -3,11 +3,11 @@
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC1XX - GPIO register definitions
* S5PC100 - GPIO register definitions
*/
#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
#include <mach/map.h>
@ -66,5 +66,5 @@
#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */

1
arch/arm/mach-s5pc100/mach-smdkc100.c
View File

@ -35,7 +35,6 @@
#include <plat/regs-serial.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-gpio.h>
#include <plat/clock.h>
#include <plat/devs.h>

5
arch/arm/plat-s5pc1xx/setup-fb-24bpp.c → arch/arm/mach-s5pc100/setup-fb-24bpp.c
View File

@ -1,9 +1,9 @@
/*
* linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
* linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
*
* Copyright 2009 Samsung Electronics
*
* Base S5PC1XX setup information for 24bpp LCD framebuffer
* Base S5PC100 setup information for 24bpp LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,7 +19,6 @@
#include <mach/map.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-s5pc1xx.h>
#define DISR_OFFSET 0x7008

4
arch/arm/plat-s5pc1xx/setup-i2c0.c → arch/arm/mach-s5pc100/setup-i2c0.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c
/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Base S5PC1XX I2C bus 0 gpio configuration
* Base S5PC100 I2C bus 0 gpio configuration
*
* Based on plat-s3c64xx/setup-i2c0.c
*

4
arch/arm/plat-s5pc1xx/setup-i2c1.c → arch/arm/mach-s5pc100/setup-i2c1.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* Base S5PC1XX I2C bus 1 gpio configuration
* Base S5PC100 I2C bus 1 gpio configuration
*
* Based on plat-s3c64xx/setup-i2c1.c
*

1
arch/arm/mach-s5pv210/Kconfig
View File

@ -12,6 +12,7 @@ if ARCH_S5PV210
config CPU_S5PV210
bool
select PLAT_S5P
select S3C_PL330_DMA
help
Enable S5PV210 CPU support

7
arch/arm/mach-s5pv210/Makefile
View File

@ -12,9 +12,14 @@ obj- :=
# Core support for S5PV210 system
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
# machine support
obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
# device support
obj-y += dev-audio.o

1183
arch/arm/mach-s5pv210/clock.c
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/mach-s5pv210/cpu.c
View File

@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic));
}
static struct sysdev_class s5pv210_sysclass = {
struct sysdev_class s5pv210_sysclass = {
.name = "s5pv210-core",
};

327
arch/arm/mach-s5pv210/dev-audio.c Normal file
View File

@ -0,0 +1,327 @@
/* linux/arch/arm/mach-s5pv210/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/gpio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5pv210_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4));
break;
case -1:
s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5pv210_cfg_i2s,
};
static struct resource s5pv210_iis0_resource[] = {
[0] = {
.start = S5PV210_PA_IIS0,
.end = S5PV210_PA_IIS0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_iis0 = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv210_iis0_resource),
.resource = s5pv210_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
static struct resource s5pv210_iis1_resource[] = {
[0] = {
.start = S5PV210_PA_IIS1,
.end = S5PV210_PA_IIS1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S1_TX,
.end = DMACH_I2S1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S1_RX,
.end = DMACH_I2S1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_iis1 = {
.name = "s3c64xx-iis",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_iis1_resource),
.resource = s5pv210_iis1_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
static struct resource s5pv210_iis2_resource[] = {
[0] = {
.start = S5PV210_PA_IIS2,
.end = S5PV210_PA_IIS2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S2_TX,
.end = DMACH_I2S2_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S2_RX,
.end = DMACH_I2S2_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_iis2 = {
.name = "s3c64xx-iis",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_iis2_resource),
.resource = s5pv210_iis2_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3));
break;
case 2:
s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5pv210_pcm_cfg_gpio,
};
static struct resource s5pv210_pcm0_resource[] = {
[0] = {
.start = S5PV210_PA_PCM0,
.end = S5PV210_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv210_pcm0_resource),
.resource = s5pv210_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv210_pcm1_resource[] = {
[0] = {
.start = S5PV210_PA_PCM1,
.end = S5PV210_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM1_TX,
.end = DMACH_PCM1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM1_RX,
.end = DMACH_PCM1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_pcm1_resource),
.resource = s5pv210_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv210_pcm2_resource[] = {
[0] = {
.start = S5PV210_PA_PCM2,
.end = S5PV210_PA_PCM2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM2_TX,
.end = DMACH_PCM2_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM2_RX,
.end = DMACH_PCM2_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5pv210_device_pcm2 = {
.name = "samsung-pcm",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_pcm2_resource),
.resource = s5pv210_pcm2_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
/* AC97 Controller platform devices */
static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4));
return 0;
}
static struct resource s5pv210_ac97_resource[] = {
[0] = {
.start = S5PV210_PA_AC97,
.end = S5PV210_PA_AC97 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_AC97_PCMOUT,
.end = DMACH_AC97_PCMOUT,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_AC97_PCMIN,
.end = DMACH_AC97_PCMIN,
.flags = IORESOURCE_DMA,
},
[3] = {
.start = DMACH_AC97_MICIN,
.end = DMACH_AC97_MICIN,
.flags = IORESOURCE_DMA,
},
[4] = {
.start = IRQ_AC97,
.end = IRQ_AC97,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_audio_pdata s3c_ac97_pdata = {
.cfg_gpio = s5pv210_ac97_cfg_gpio,
};
static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv210_device_ac97 = {
.name = "s3c-ac97",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv210_ac97_resource),
.resource = s5pv210_ac97_resource,
.dev = {
.platform_data = &s3c_ac97_pdata,
.dma_mask = &s5pv210_ac97_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};

168
arch/arm/mach-s5pv210/dma.c Normal file
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@ -0,0 +1,168 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv210_pdma0_resource[] = {
[0] = {
.start = S5PV210_PA_PDMA0,
.end = S5PV210_PA_PDMA0 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA0,
.end = IRQ_PDMA0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_SPI1_RX,
[19] = DMACH_SPI1_TX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_AC97_MICIN,
[23] = DMACH_AC97_PCMIN,
[24] = DMACH_AC97_PCMOUT,
[25] = DMACH_MAX,
[26] = DMACH_PWM,
[27] = DMACH_SPDIF,
[28] = DMACH_MAX,
[29] = DMACH_MAX,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
};
static struct platform_device s5pv210_device_pdma0 = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
.resource = s5pv210_pdma0_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma0_pdata,
},
};
static struct resource s5pv210_pdma1_resource[] = {
[0] = {
.start = S5PV210_PA_PDMA1,
.end = S5PV210_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA1,
.end = IRQ_PDMA1,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_I2S2_RX,
[15] = DMACH_I2S2_TX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_SPI1_RX,
[19] = DMACH_SPI1_TX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_PCM0_RX,
[23] = DMACH_PCM0_TX,
[24] = DMACH_PCM1_RX,
[25] = DMACH_PCM1_TX,
[26] = DMACH_MSM_REQ0,
[27] = DMACH_MSM_REQ1,
[28] = DMACH_MSM_REQ2,
[29] = DMACH_MSM_REQ3,
[30] = DMACH_PCM2_RX,
[31] = DMACH_PCM2_TX,
},
};
static struct platform_device s5pv210_device_pdma1 = {
.name = "s3c-pl330",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_pdma1_resource),
.resource = s5pv210_pdma1_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma1_pdata,
},
};
static struct platform_device *s5pv210_dmacs[] __initdata = {
&s5pv210_device_pdma0,
&s5pv210_device_pdma1,
};
static int __init s5pv210_dma_init(void)
{
platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs));
return 0;
}
arch_initcall(s5pv210_dma_init);

261
arch/arm/mach-s5pv210/gpiolib.c Normal file
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@ -0,0 +1,261 @@
/* linux/arch/arm/mach-s5pv210/gpiolib.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/map.h>
static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
/* GPIO bank's base address given the index of the bank in the
* list of all gpio banks.
*/
#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
/*
* Following are the gpio banks in v210.
*
* The 'config' member when left to NULL, is initialized to the default
* structure gpio_cfg in the init function below.
*
* The 'base' member is also initialized in the init function below.
* Note: The initialization of 'base' member of s3c_gpio_chip structure
* uses the above macro and depends on the banks being listed in order here.
*/
static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
{
.chip = {
.base = S5PV210_GPA0(0),
.ngpio = S5PV210_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.chip = {
.base = S5PV210_GPA1(0),
.ngpio = S5PV210_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.chip = {
.base = S5PV210_GPB(0),
.ngpio = S5PV210_GPIO_B_NR,
.label = "GPB",
},
}, {
.chip = {
.base = S5PV210_GPC0(0),
.ngpio = S5PV210_GPIO_C0_NR,
.label = "GPC0",
},
}, {
.chip = {
.base = S5PV210_GPC1(0),
.ngpio = S5PV210_GPIO_C1_NR,
.label = "GPC1",
},
}, {
.chip = {
.base = S5PV210_GPD0(0),
.ngpio = S5PV210_GPIO_D0_NR,
.label = "GPD0",
},
}, {
.chip = {
.base = S5PV210_GPD1(0),
.ngpio = S5PV210_GPIO_D1_NR,
.label = "GPD1",
},
}, {
.chip = {
.base = S5PV210_GPE0(0),
.ngpio = S5PV210_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.chip = {
.base = S5PV210_GPE1(0),
.ngpio = S5PV210_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.chip = {
.base = S5PV210_GPF0(0),
.ngpio = S5PV210_GPIO_F0_NR,
.label = "GPF0",
},
}, {
.chip = {
.base = S5PV210_GPF1(0),
.ngpio = S5PV210_GPIO_F1_NR,
.label = "GPF1",
},
}, {
.chip = {
.base = S5PV210_GPF2(0),
.ngpio = S5PV210_GPIO_F2_NR,
.label = "GPF2",
},
}, {
.chip = {
.base = S5PV210_GPF3(0),
.ngpio = S5PV210_GPIO_F3_NR,
.label = "GPF3",
},
}, {
.chip = {
.base = S5PV210_GPG0(0),
.ngpio = S5PV210_GPIO_G0_NR,
.label = "GPG0",
},
}, {
.chip = {
.base = S5PV210_GPG1(0),
.ngpio = S5PV210_GPIO_G1_NR,
.label = "GPG1",
},
}, {
.chip = {
.base = S5PV210_GPG2(0),
.ngpio = S5PV210_GPIO_G2_NR,
.label = "GPG2",
},
}, {
.chip = {
.base = S5PV210_GPG3(0),
.ngpio = S5PV210_GPIO_G3_NR,
.label = "GPG3",
},
}, {
.chip = {
.base = S5PV210_GPI(0),
.ngpio = S5PV210_GPIO_I_NR,
.label = "GPI",
},
}, {
.chip = {
.base = S5PV210_GPJ0(0),
.ngpio = S5PV210_GPIO_J0_NR,
.label = "GPJ0",
},
}, {
.chip = {
.base = S5PV210_GPJ1(0),
.ngpio = S5PV210_GPIO_J1_NR,
.label = "GPJ1",
},
}, {
.chip = {
.base = S5PV210_GPJ2(0),
.ngpio = S5PV210_GPIO_J2_NR,
.label = "GPJ2",
},
}, {
.chip = {
.base = S5PV210_GPJ3(0),
.ngpio = S5PV210_GPIO_J3_NR,
.label = "GPJ3",
},
}, {
.chip = {
.base = S5PV210_GPJ4(0),
.ngpio = S5PV210_GPIO_J4_NR,
.label = "GPJ4",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_MP01(0),
.ngpio = S5PV210_GPIO_MP01_NR,
.label = "MP01",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_MP02(0),
.ngpio = S5PV210_GPIO_MP02_NR,
.label = "MP02",
},
}, {
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_MP03(0),
.ngpio = S5PV210_GPIO_MP03_NR,
.label = "MP03",
},
}, {
.base = (S5P_VA_GPIO + 0xC00),
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_GPH0(0),
.ngpio = S5PV210_GPIO_H0_NR,
.label = "GPH0",
},
}, {
.base = (S5P_VA_GPIO + 0xC20),
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_GPH1(0),
.ngpio = S5PV210_GPIO_H1_NR,
.label = "GPH1",
},
}, {
.base = (S5P_VA_GPIO + 0xC40),
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_GPH2(0),
.ngpio = S5PV210_GPIO_H2_NR,
.label = "GPH2",
},
}, {
.base = (S5P_VA_GPIO + 0xC60),
.config = &gpio_cfg_noint,
.chip = {
.base = S5PV210_GPH3(0),
.ngpio = S5PV210_GPIO_H3_NR,
.label = "GPH3",
},
},
};
static __init int s5pv210_gpiolib_init(void)
{
struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
int i = 0;
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
chip->config = &gpio_cfg;
if (chip->base == NULL)
chip->base = S5PV210_BANK_BASE(i);
}
samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
return 0;
}
core_initcall(s5pv210_gpiolib_init);

26
arch/arm/mach-s5pv210/include/mach/dma.h Normal file
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@ -0,0 +1,26 @@
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */

18
arch/arm/mach-s5pv210/include/mach/gpio.h
View File

@ -18,6 +18,8 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
/* GPIO bank sizes */
#define S5PV210_GPIO_A0_NR (8)
#define S5PV210_GPIO_A1_NR (4)
@ -47,6 +49,10 @@
#define S5PV210_GPIO_J3_NR (8)
#define S5PV210_GPIO_J4_NR (5)
#define S5PV210_GPIO_MP01_NR (8)
#define S5PV210_GPIO_MP02_NR (4)
#define S5PV210_GPIO_MP03_NR (8)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
@ -85,6 +91,9 @@ enum s5p_gpio_number {
S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
};
/* S5PV210 GPIO number definitions */
@ -115,13 +124,16 @@ enum s5p_gpio_number {
#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
/* the end of the S5PV210 specific gpios */
#define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1)
#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
#define S3C_GPIO_END S5PV210_GPIO_END
/* define the number of gpios we need to the one after the GPJ4() range */
#define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \
/* define the number of gpios we need to the one after the MP03() range */
#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>

17
arch/arm/mach-s5pv210/include/mach/map.h
View File

@ -43,6 +43,10 @@
#define S5PV210_PA_SROMC (0xE8000000)
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_VIC0 (0xF2000000)
#define S5P_PA_VIC0 S5PV210_PA_VIC0
@ -58,6 +62,19 @@
#define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
/* I2S */
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
/* PCM */
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
/* AC97 */
#define S5PV210_PA_AC97 0xE2200000
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV210_PA_UART
#define S3C_PA_IIC S5PV210_PA_IIC0

23
arch/arm/mach-s5pv210/include/mach/pwm-clock.h
View File

@ -1,13 +1,14 @@
/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5PV210 - pwm clock and timer support
*
@ -21,14 +22,14 @@
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0.
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C2410_TCFG1_MUX_TCLK;
return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
return 1 << tcfg1;
}
/**
@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 0;
return 1;
}
/**
@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div) - 1;
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */

2
arch/arm/mach-s5pv210/mach-smdkc110.c
View File

@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
};
static struct platform_device *smdkc110_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
};
static void __init smdkc110_map_io(void)

2
arch/arm/mach-s5pv210/mach-smdkv210.c
View File

@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
};
static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
};
static void __init smdkv210_map_io(void)

25
arch/arm/mach-s5pv210/setup-i2c0.c Normal file
View File

@ -0,0 +1,25 @@
/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
/* Will be populated later */
}

5
arch/arm/mm/mmu.c
View File

@ -870,9 +870,10 @@ void __init reserve_node_zero(pg_data_t *pgdat)
if (machine_is_p720t())
res_size = 0x00014000;
/* H1940 and RX3715 need to reserve this for suspend */
/* H1940, RX3715 and RX1950 need to reserve this for suspend */
if (machine_is_h1940() || machine_is_rx3715()) {
if (machine_is_h1940() || machine_is_rx3715()
|| machine_is_rx1950()) {
reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
BOOTMEM_DEFAULT);
reserve_bootmem_node(pgdat, 0x30081000, 0x1000,

5
arch/arm/plat-s3c24xx/Kconfig
View File

@ -164,4 +164,9 @@ config S3C24XX_SIMTEC_AUDIO
help
Add audio devices for common Simtec S3C24XX boards
config S3C2410_SETUP_TS
bool
help
Compile in platform device definition for Samsung TouchScreen.
endif

1
arch/arm/plat-s3c24xx/Makefile
View File

@ -38,6 +38,7 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
# device specific setup and/or initialisation
obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
obj-$(CONFIG_S3C2410_SETUP_TS) += setup-ts.o
# SPI gpio central GPIO functions

22
arch/arm/plat-s3c24xx/devs.c
View File

@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -38,8 +39,7 @@
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/regs-spi.h>
#include <mach/ts.h>
#include <plat/ts.h>
/* Serial port registrations */
@ -149,10 +149,14 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
{
struct s3c2410fb_mach_info *npd;
npd = kmalloc(sizeof(*npd), GFP_KERNEL);
npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
if (npd) {
memcpy(npd, pd, sizeof(*npd));
s3c_device_lcd.dev.platform_data = npd;
npd->displays = kmemdup(pd->displays,
sizeof(struct s3c2410fb_display) * npd->num_displays,
GFP_KERNEL);
if (!npd->displays)
printk(KERN_ERR "no memory for LCD display data\n");
} else {
printk(KERN_ERR "no memory for LCD platform data\n");
}
@ -338,14 +342,6 @@ struct platform_device s3c_device_adc = {
.resource = s3c_adc_resource,
};
/* HWMON */
struct platform_device s3c_device_hwmon = {
.name = "s3c-hwmon",
.id = -1,
.dev.parent = &s3c_device_adc.dev,
};
/* SDI */
static struct resource s3c_sdi_resource[] = {
@ -371,7 +367,7 @@ struct platform_device s3c_device_sdi = {
EXPORT_SYMBOL(s3c_device_sdi);
void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
{
struct s3c24xx_mci_pdata *npd;

2
arch/arm/plat-s3c24xx/dma.c
View File

@ -1104,7 +1104,7 @@ EXPORT_SYMBOL(s3c2410_dma_config);
* devaddr: physical address of the source
*/
int s3c2410_dma_devconfig(int channel,
int s3c2410_dma_devconfig(unsigned int channel,
enum s3c2410_dmasrc source,
unsigned long devaddr)
{

8
arch/arm/plat-s3c24xx/gpio.c
View File

@ -34,6 +34,8 @@
#include <mach/regs-gpio.h>
#include <plat/gpio-core.h>
/* gpiolib wrappers until these are totally eliminated */
void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
@ -68,10 +70,10 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin);
unsigned int s3c2410_gpio_getpin(unsigned int pin)
{
void __iomem *base = S3C24XX_GPIO_BASE(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin);
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long offs = pin - chip->chip.base;
return __raw_readl(base + 0x04) & (1<< offs);
return __raw_readl(chip->base + 0x04) & (1<< offs);
}
EXPORT_SYMBOL(s3c2410_gpio_getpin);

34
arch/arm/plat-s3c24xx/setup-ts.c Normal file
View File

@ -0,0 +1,34 @@
/* linux/arch/arm/plat-s3c24xx/setup-ts.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Based on S3C24XX setup for i2c device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
struct platform_device; /* don't need the contents */
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
/**
* s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems
*
* Configure the GPIO for the S3C2410 system, where we have external FETs
* connected to the device (later systems such as the S3C2440 integrate
* these into the device).
*/
void s3c24xx_ts_cfg_gpio(struct platform_device *dev)
{
s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON);
s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON);
s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON);
s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON);
}

1
arch/arm/plat-s5p/Kconfig
View File

@ -13,6 +13,7 @@ config PLAT_S5P
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S5P_GPIO_DRVSTR
select SAMSUNG_GPIOLIB_4BIT
select S3C_GPIO_CFG_S3C64XX
select S3C_GPIO_PULL_UPDOWN

1
arch/arm/plat-s5p/Makefile
View File

@ -16,4 +16,3 @@ obj-y += dev-uart.o
obj-y += cpu.o
obj-y += clock.o
obj-y += irq.o
obj-y += setup-i2c0.o

15
arch/arm/plat-s5p/clock.c
View File

@ -33,7 +33,12 @@ struct clk clk_ext_xtal_mux = {
.id = -1,
};
static struct clk s5p_clk_27m = {
struct clk clk_xusbxti = {
.name = "xusbxti",
.id = -1,
};
struct clk s5p_clk_27m = {
.name = "clk_27m",
.id = -1,
.rate = 27000000,
@ -69,6 +74,13 @@ struct clk clk_fout_epll = {
.ctrlbit = (1 << 31),
};
/* VPLL clock output */
struct clk clk_fout_vpll = {
.name = "fout_vpll",
.id = -1,
.ctrlbit = (1 << 31),
};
/* ARM clock */
struct clk clk_arm = {
.name = "armclk",
@ -133,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = {
&clk_fout_apll,
&clk_fout_mpll,
&clk_fout_epll,
&clk_fout_vpll,
&clk_arm,
&clk_vpll,
};

2
arch/arm/plat-s5p/include/plat/irqs.h
View File

@ -79,7 +79,7 @@
#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x))
#define S5P_TIMER_IRQ(x) (11 + (x))
#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
#define IRQ_TIMER1 S5P_TIMER_IRQ(1)

22
arch/arm/plat-s5p/include/plat/pll.h
View File

@ -81,3 +81,25 @@ static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
return result;
}
#define PLL65XX_MDIV_MASK (0x3FF)
#define PLL65XX_PDIV_MASK (0x3F)
#define PLL65XX_SDIV_MASK (0x7)
#define PLL65XX_MDIV_SHIFT (16)
#define PLL65XX_PDIV_SHIFT (8)
#define PLL65XX_SDIV_SHIFT (0)
static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
{
u32 mdiv, pdiv, sdiv;
u64 fvco = baseclk;
mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
fvco *= mdiv;
do_div(fvco, (pdiv << sdiv));
return (unsigned long)fvco;
}

4
arch/arm/plat-s5p/include/plat/s5p-clock.h
View File

@ -21,12 +21,16 @@
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fin_vpll clk_ext_xtal_mux
#define clk_fin_hpll clk_ext_xtal_mux
extern struct clk clk_ext_xtal_mux;
extern struct clk clk_xusbxti;
extern struct clk clk_48m;
extern struct clk s5p_clk_27m;
extern struct clk clk_fout_apll;
extern struct clk clk_fout_mpll;
extern struct clk clk_fout_epll;
extern struct clk clk_fout_vpll;
extern struct clk clk_arm;
extern struct clk clk_vpll;

22
arch/arm/plat-s5pc1xx/Kconfig
View File

@ -16,9 +16,10 @@ config PLAT_S5PC1XX
select SAMSUNG_IRQ_VIC_TIMER
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S5P_GPIO_DRVSTR
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
select S5P_GPIO_CFG_S5PC1XX
select SAMSUNG_GPIOLIB_4BIT
help
Base platform code for any Samsung S5PC1XX device
@ -38,25 +39,6 @@ config CPU_S5PC100_CLOCK
# platform specific device setup
config S5PC1XX_SETUP_FB_24BPP
bool
help
Common setup code for S5PC1XX with an 24bpp RGB display helper.
config S5PC1XX_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S5PC1XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S5PC1XX_SETUP_SDHCI_GPIO
bool
help

7
arch/arm/plat-s5pc1xx/Makefile
View File

@ -13,9 +13,8 @@ obj- :=
obj-y += dev-uart.o
obj-y += cpu.o
obj-y += irq.o irq-gpio.o irq-eint.o
obj-y += irq.o
obj-y += clock.o
obj-y += gpiolib.o
# CPU support
@ -24,8 +23,4 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
# Device setup
obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

62
arch/arm/plat-s5pc1xx/gpio-config.c
View File

@ -1,62 +0,0 @@
/* linux/arch/arm/plat-s5pc1xx/gpio-config.c
*
* Copyright 2009 Samsung Electronics
*
* S5PC1XX GPIO Configuration.
*
* Based on plat-s3c64xx/gpio-config.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <plat/gpio-core.h>
#include <plat/gpio-cfg-s5pc1xx.h>
s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
int shift = off * 2;
u32 drvstr;
if (!chip)
return -EINVAL;
reg = chip->base + 0x0C;
drvstr = __raw_readl(reg);
drvstr = 0xffff & (0x3 << shift);
drvstr = drvstr >> shift;
return (__force s5p_gpio_drvstr_t)drvstr;
}
EXPORT_SYMBOL(s5p_gpio_get_drvstr);
int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
s5p_gpio_drvstr_t drvstr)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
void __iomem *reg;
int shift = off * 2;
u32 tmp;
if (!chip)
return -EINVAL;
reg = chip->base + 0x0C;
tmp = __raw_readl(reg);
tmp |= drvstr << shift;
__raw_writel(tmp, reg);
return 0;
}
EXPORT_SYMBOL(s5p_gpio_set_drvstr);

32
arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
View File

@ -1,32 +0,0 @@
/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h
*
* Copyright 2009 Samsung Electronic
*
* S5PC1XX Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
#ifndef __GPIO_CFG_S5PC1XX_H
#define __GPIO_CFG_S5PC1XX_H __FILE__
typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
#define S5P_GPIO_DRVSTR_LV1 0x00
#define S5P_GPIO_DRVSTR_LV2 0x01
#define S5P_GPIO_DRVSTR_LV3 0x10
#define S5P_GPIO_DRVSTR_LV4 0x11
extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off);
extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
s5p_gpio_drvstr_t drvstr);
#endif /* __GPIO_CFG_S5PC1XX_H */

38
arch/arm/plat-samsung/Kconfig
View File

@ -90,12 +90,6 @@ config S3C_GPIO_CFG_S3C64XX
Internal configuration to enable S3C64XX style GPIO configuration
functions.
config S5P_GPIO_CFG_S5PC1XX
bool
help
Internal configuration to enable S5PC1XX style GPIO configuration
functions.
config S3C_GPIO_PULL_UPDOWN
bool
help
@ -111,6 +105,12 @@ config S3C_GPIO_PULL_UP
help
Internal configuration to enable the correct GPIO pull helper
config S5P_GPIO_DRVSTR
bool
help
Internal configuration to get and set correct GPIO driver strength
helper
config SAMSUNG_GPIO_EXTRA
int "Number of additional GPIO pins"
default 0
@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2
help
Compile in platform device definitions for HSMMC channel 2
config S3C_DEV_HWMON
bool
help
Compile in platform device definitions for HWMON
config S3C_DEV_I2C1
bool
help
@ -185,12 +190,27 @@ config S3C_DEV_NAND
help
Compile in platform device definition for NAND controller
config S3C_DEV_RTC
bool
help
Complie in platform device definition for RTC
config SAMSUNG_DEV_ADC
bool
help
Compile in platform device definition for ADC controller
config S3C64XX_DEV_SPI
bool
help
Compile in platform device definitions for S3C64XX's type
SPI controllers.
config SAMSUNG_DEV_TS
bool
help
Common in platform device definitions for touchscreen device
# DMA
config S3C_DMA
@ -198,6 +218,12 @@ config S3C_DMA
help
Internal configuration for S3C DMA core
config S3C_PL330_DMA
bool
select PL330
help
S3C DMA API Driver for PL330 DMAC.
comment "Power management"
config SAMSUNG_PM_DEBUG

7
arch/arm/plat-samsung/Makefile
View File

@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o
obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
@ -40,11 +41,17 @@ obj-y += dev-uart.o
obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o
obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o
obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o
obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o
obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o
# DMA support
obj-$(CONFIG_S3C_DMA) += dma.o
obj-$(CONFIG_S3C_PL330_DMA) += s3c-pl330.o
# PM support
obj-$(CONFIG_PM) += pm.o

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