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clk: ls1x: Update relationship among all clocks 

- Add clock lookups for APB devices.
 - Update clock relationship to make it more exact and clear.
                                 _____
         _______________________|     |
 OSC ___/                       | MUX |___ XXX CLK
        \___ PLL ___ XXX DIV ___|     |
                                |_____|

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: mturquette@linaro.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8026/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kelvin Cheung 2014-10-10 11:42:51 +08:00 committed by Ralf Baechle
parent c5d58e9e79
commit 3526f74fa9
1 changed files with 77 additions and 26 deletions
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99
drivers/clk/clk-ls1x.c
View File

@ -15,7 +15,8 @@
#include <loongson1.h>
#define OSC 33
#define OSC (33 * 1000000)
#define DIV_APB 2
static DEFINE_SPINLOCK(_lock);
@ -34,8 +35,7 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
u32 pll, rate;
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
rate = ((12 + (pll & 0x3f)) * 1000000) +
((((pll >> 8) & 0x3ff) * 1000000) >> 10);
rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10);
rate *= OSC;
rate >>= 1;
@ -48,8 +48,10 @@ static const struct clk_ops ls1x_pll_clk_ops = {
.recalc_rate = ls1x_pll_recalc_rate,
};
static struct clk * __init clk_register_pll(struct device *dev,
const char *name, const char *parent_name, unsigned long flags)
static struct clk *__init clk_register_pll(struct device *dev,
const char *name,
const char *parent_name,
unsigned long flags)
{
struct clk_hw *hw;
struct clk *clk;
@ -78,34 +80,83 @@ static struct clk * __init clk_register_pll(struct device *dev,
return clk;
}
static const char const *cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };
static const char const *ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };
static const char const *dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
void __init ls1x_clk_init(void)
{
struct clk *clk;
clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
clk_prepare_enable(clk);
clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT,
OSC);
clk_register_clkdev(clk, "osc_33m_clk", NULL);
clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "cpu", NULL);
/* clock derived from 33 MHz OSC clk */
clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);
clk_register_clkdev(clk, "pll_clk", NULL);
clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
/* clock derived from PLL clk */
/* _____
* _______________________| |
* OSC ___/ | MUX |___ CPU CLK
* \___ PLL ___ CPU DIV ___| |
* |_____|
*/
clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk",
CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
DIV_CPU_SHIFT, DIV_CPU_WIDTH,
CLK_DIVIDER_ONE_BASED |
CLK_DIVIDER_ROUND_CLOSEST, &_lock);
clk_register_clkdev(clk, "cpu_clk_div", NULL);
clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
ARRAY_SIZE(cpu_parents),
CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock);
clk_register_clkdev(clk, "cpu_clk", NULL);
/* _____
* _______________________| |
* OSC ___/ | MUX |___ DC CLK
* \___ PLL ___ DC DIV ___| |
* |_____|
*/
clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",
0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "dc", NULL);
clk_register_clkdev(clk, "dc_clk_div", NULL);
clk = clk_register_mux(NULL, "dc_clk", dc_parents,
ARRAY_SIZE(dc_parents),
CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock);
clk_register_clkdev(clk, "dc_clk", NULL);
clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "ahb", NULL);
/* _____
* _______________________| |
* OSC ___/ | MUX |___ DDR CLK
* \___ PLL ___ DDR DIV ___| |
* |_____|
*/
clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",
0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
&_lock);
clk_register_clkdev(clk, "ahb_clk_div", NULL);
clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
ARRAY_SIZE(ahb_parents),
CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV,
BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock);
clk_register_clkdev(clk, "ahb_clk", NULL);
clk_register_clkdev(clk, "stmmaceth", NULL);
clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
clk_prepare_enable(clk);
clk_register_clkdev(clk, "apb", NULL);
/* clock derived from AHB clk */
/* APB clk is always half of the AHB clk */
clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
DIV_APB);
clk_register_clkdev(clk, "apb_clk", NULL);
clk_register_clkdev(clk, "ls1x_i2c", NULL);
clk_register_clkdev(clk, "ls1x_pwmtimer", NULL);
clk_register_clkdev(clk, "ls1x_spi", NULL);
clk_register_clkdev(clk, "ls1x_wdt", NULL);
clk_register_clkdev(clk, "serial8250", NULL);
}