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drm/nouveau/mmu: index engref by subdev type 

None of the chipsets we use this on have instanced engines, so this is fine.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-06 21:43:22 +10:00
parent 6dd123ba8a
commit 353108a49f
2 changed files with 3 additions and 3 deletions
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4
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
View File

@ -118,7 +118,7 @@ nvkm_fifo_chan_child_del(struct nvkm_oproxy *base)
chan->func->engine_dtor(chan, engine);
nvkm_object_del(&engn->object);
if (chan->vmm)
atomic_dec(&chan->vmm->engref[engine->subdev.index]);
atomic_dec(&chan->vmm->engref[engine->subdev.type]);
}
}
@ -152,7 +152,7 @@ nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size,
};
if (chan->vmm)
atomic_inc(&chan->vmm->engref[engine->subdev.index]);
atomic_inc(&chan->vmm->engref[engine->subdev.type]);
if (engine->func->fifo.cclass) {
ret = engine->func->fifo.cclass(chan, &cclass,

2
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c
View File

@ -207,7 +207,7 @@ nv50_vmm_flush(struct nvkm_vmm *vmm, int level)
case NVKM_ENGINE_MSVLD : id = 0x09; break;
case NVKM_ENGINE_CIPHER:
case NVKM_ENGINE_SEC : id = 0x0a; break;
case NVKM_ENGINE_CE0 : id = 0x0d; break;
case NVKM_ENGINE_CE : id = 0x0d; break;
default:
continue;
}