mirror of https://gitee.com/openkylin/linux.git
drm/radeon: add get_allowed_info_register for CIK
Registers that can be fetched from the info ioctl. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4af692f6e3
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@ -141,6 +141,39 @@ static void cik_fini_cg(struct radeon_device *rdev);
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static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
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static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
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bool enable);
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bool enable);
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/**
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* cik_get_allowed_info_register - fetch the register for the info ioctl
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*
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* @rdev: radeon_device pointer
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* @reg: register offset in bytes
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* @val: register value
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*
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* Returns 0 for success or -EINVAL for an invalid register
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*
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*/
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int cik_get_allowed_info_register(struct radeon_device *rdev,
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u32 reg, u32 *val)
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{
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switch (reg) {
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case GRBM_STATUS:
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case GRBM_STATUS2:
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case GRBM_STATUS_SE0:
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case GRBM_STATUS_SE1:
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case GRBM_STATUS_SE2:
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case GRBM_STATUS_SE3:
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case SRBM_STATUS:
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case SRBM_STATUS2:
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case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
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case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
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case UVD_STATUS:
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/* TODO VCE */
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*val = RREG32(reg);
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return 0;
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default:
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return -EINVAL;
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}
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}
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/* get temperature in millidegrees */
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/* get temperature in millidegrees */
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int ci_get_temp(struct radeon_device *rdev)
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int ci_get_temp(struct radeon_device *rdev)
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{
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{
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@ -2088,6 +2088,8 @@
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# define CLK_OD(x) ((x) << 6)
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# define CLK_OD(x) ((x) << 6)
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# define CLK_OD_MASK (0x1f << 6)
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# define CLK_OD_MASK (0x1f << 6)
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#define UVD_STATUS 0xf6bc
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/* UVD clocks */
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/* UVD clocks */
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#define CG_DCLK_CNTL 0xC050009C
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#define CG_DCLK_CNTL 0xC050009C
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@ -2075,6 +2075,7 @@ static struct radeon_asic ci_asic = {
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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.get_xclk = &cik_get_xclk,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.get_allowed_info_register = cik_get_allowed_info_register,
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.gart = {
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.gart = {
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.get_page_entry = &rs600_gart_get_page_entry,
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.get_page_entry = &rs600_gart_get_page_entry,
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@ -2187,6 +2188,7 @@ static struct radeon_asic kv_asic = {
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
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.get_xclk = &cik_get_xclk,
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.get_xclk = &cik_get_xclk,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.get_gpu_clock_counter = &cik_get_gpu_clock_counter,
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.get_allowed_info_register = cik_get_allowed_info_register,
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.gart = {
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.gart = {
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.tlb_flush = &cik_pcie_gart_tlb_flush,
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.get_page_entry = &rs600_gart_get_page_entry,
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.get_page_entry = &rs600_gart_get_page_entry,
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@ -865,6 +865,8 @@ void cik_sdma_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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struct radeon_ring *ring);
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int ci_get_temp(struct radeon_device *rdev);
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int ci_get_temp(struct radeon_device *rdev);
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int kv_get_temp(struct radeon_device *rdev);
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int kv_get_temp(struct radeon_device *rdev);
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int cik_get_allowed_info_register(struct radeon_device *rdev,
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u32 reg, u32 *val);
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int ci_dpm_init(struct radeon_device *rdev);
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int ci_dpm_init(struct radeon_device *rdev);
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int ci_dpm_enable(struct radeon_device *rdev);
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int ci_dpm_enable(struct radeon_device *rdev);
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