mirror of https://gitee.com/openkylin/linux.git
media: ccs-pll: Fix VT post-PLL divisor calculation
The PLL calculator only searched even total divisor values apart from one, but this is wrong: the total divisor is odd in cases where system divisor is one. Fix this by including odd total PLL values where system divisor is one to the search. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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@ -347,14 +347,16 @@ ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
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* into a value which is not smaller than div, the desired
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* into a value which is not smaller than div, the desired
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* divisor.
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* divisor.
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*/
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*/
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for (vt_div = min_vt_div; vt_div <= max_vt_div;
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for (vt_div = min_vt_div; vt_div <= max_vt_div; vt_div++) {
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vt_div += 2 - (vt_div & 1)) {
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uint16_t __max_sys_div = vt_div & 1 ? 1 : max_sys_div;
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for (sys_div = min_sys_div;
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sys_div <= max_sys_div;
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for (sys_div = min_sys_div; sys_div <= __max_sys_div;
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sys_div += 2 - (sys_div & 1)) {
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sys_div += 2 - (sys_div & 1)) {
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uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
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uint16_t pix_div;
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uint16_t rounded_div;
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uint16_t rounded_div;
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pix_div = DIV_ROUND_UP(vt_div, sys_div);
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if (pix_div < lim->vt_bk.min_pix_clk_div
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if (pix_div < lim->vt_bk.min_pix_clk_div
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|| pix_div > lim->vt_bk.max_pix_clk_div) {
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|| pix_div > lim->vt_bk.max_pix_clk_div) {
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dev_dbg(dev,
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dev_dbg(dev,
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