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drm/i915: Clean up L3 SQC register field definitions 

No need for hard-coding the register value, the corresponding fields are
defined properly in BSpec.

No functional change.

v2:
- Rebased on BXT L3 SQC tuning patch merged meanwhile.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-3-git-send-email-imre.deak@intel.com
This commit is contained in:
Imre Deak 2016-05-03 15:54:20 +03:00
parent 48e5d68d28
commit 36579cb63b
3 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_reg.h
View File

@ -6091,8 +6091,8 @@ enum skl_disp_power_wells {
#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
#define GEN8_L3SQCREG1 _MMIO(0xB100) #define GEN8_L3SQCREG1 _MMIO(0xB100)
#define BDW_WA_L3SQCREG1_DEFAULT 0x784000 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
#define BXT_WA_L3SQCREG1_DEFAULT 0xF84000 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define GEN7_L3CNTLREG1 _MMIO(0xB01C) #define GEN7_L3CNTLREG1 _MMIO(0xB01C)
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C

3
drivers/gpu/drm/i915/intel_pm.c
View File

@ -6737,7 +6737,8 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
*/ */
misccpctl = I915_READ(GEN7_MISCCPCTL); misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(30) |
L3_HIGH_PRIO_CREDITS(2));
/* /*
* Wait at least 100 clocks before re-enabling clock gating. See * Wait at least 100 clocks before re-enabling clock gating. See
* the definition of L3SQCREG1 in BSpec. * the definition of L3SQCREG1 in BSpec.

3
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -1182,7 +1182,8 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaProgramL3SqcReg1DefaultForPerf:bxt */ /* WaProgramL3SqcReg1DefaultForPerf:bxt */
if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT); I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
L3_HIGH_PRIO_CREDITS(2));
return 0; return 0;
} }