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media: omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode
ISP CSI1 module needs all the bits correctly set to work. Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # on Beagleboard-xM + MPT9P031 Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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@ -213,14 +213,17 @@ static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
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struct isp_device *isp = to_isp_device(ccp2);
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u32 val;
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/* CCP2B mode */
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val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
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ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;
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ISPCCP2_CTRL_MODE;
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/* Data/strobe physical layer */
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BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
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buscfg->phy_layer);
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BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT,
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ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode);
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BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
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buscfg->strobe_clk_pol);
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BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT,
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ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol);
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isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
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val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
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@ -87,6 +87,8 @@
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#define ISPCCP2_CTRL_PHY_SEL_MASK 0x1
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#define ISPCCP2_CTRL_PHY_SEL_SHIFT 1
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#define ISPCCP2_CTRL_IO_OUT_SEL (1 << 2)
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#define ISPCCP2_CTRL_IO_OUT_SEL_MASK 0x1
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#define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT 2
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#define ISPCCP2_CTRL_MODE (1 << 4)
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#define ISPCCP2_CTRL_VP_CLK_FORCE_ON (1 << 9)
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#define ISPCCP2_CTRL_INV (1 << 10)
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@ -94,6 +96,8 @@
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#define ISPCCP2_CTRL_INV_SHIFT 10
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#define ISPCCP2_CTRL_VP_ONLY_EN (1 << 11)
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#define ISPCCP2_CTRL_VP_CLK_POL (1 << 12)
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#define ISPCCP2_CTRL_VP_CLK_POL_MASK 0x1
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#define ISPCCP2_CTRL_VP_CLK_POL_SHIFT 12
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#define ISPCCP2_CTRL_VPCLK_DIV_SHIFT 15
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#define ISPCCP2_CTRL_VPCLK_DIV_MASK 0x1ffff /* [31:15] */
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#define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT 8 /* 3430 bits */
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