mirror of https://gitee.com/openkylin/linux.git
sfc: move channel interrupt management code
Small code styling fixes included. Signed-off-by: Alexandru-Mihai Maftei <amaftei@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Maftei (amaftei)
David S. Miller
parent
8397548507
commit
37c45a4e33
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@ -96,17 +96,6 @@ static unsigned int rx_irq_mod_usec = 60;
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*/
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*/
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static unsigned int tx_irq_mod_usec = 150;
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static unsigned int tx_irq_mod_usec = 150;
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/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
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* i.e. the number of CPUs among which we may distribute simultaneous
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* interrupt handling.
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*
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* Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
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* The default (0) means to assign an interrupt to each core.
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*/
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static unsigned int rss_cpus;
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module_param(rss_cpus, uint, 0444);
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MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
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static bool phy_flash_cfg;
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static bool phy_flash_cfg;
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module_param(phy_flash_cfg, bool, 0644);
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module_param(phy_flash_cfg, bool, 0644);
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MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
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MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
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@ -450,311 +439,6 @@ void efx_set_default_rx_indir_table(struct efx_nic *efx,
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ethtool_rxfh_indir_default(i, efx->rss_spread);
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ethtool_rxfh_indir_default(i, efx->rss_spread);
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}
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}
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static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
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{
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cpumask_var_t thread_mask;
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unsigned int count;
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int cpu;
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if (rss_cpus) {
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count = rss_cpus;
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} else {
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if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
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netif_warn(efx, probe, efx->net_dev,
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"RSS disabled due to allocation failure\n");
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return 1;
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}
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count = 0;
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for_each_online_cpu(cpu) {
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if (!cpumask_test_cpu(cpu, thread_mask)) {
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++count;
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cpumask_or(thread_mask, thread_mask,
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topology_sibling_cpumask(cpu));
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}
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}
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free_cpumask_var(thread_mask);
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}
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if (count > EFX_MAX_RX_QUEUES) {
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netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn,
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"Reducing number of rx queues from %u to %u.\n",
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count, EFX_MAX_RX_QUEUES);
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count = EFX_MAX_RX_QUEUES;
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}
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/* If RSS is requested for the PF *and* VFs then we can't write RSS
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* table entries that are inaccessible to VFs
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*/
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#ifdef CONFIG_SFC_SRIOV
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if (efx->type->sriov_wanted) {
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if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
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count > efx_vf_size(efx)) {
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netif_warn(efx, probe, efx->net_dev,
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"Reducing number of RSS channels from %u to %u for "
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"VF support. Increase vf-msix-limit to use more "
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"channels on the PF.\n",
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count, efx_vf_size(efx));
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count = efx_vf_size(efx);
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}
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}
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#endif
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return count;
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}
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static int efx_allocate_msix_channels(struct efx_nic *efx,
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unsigned int max_channels,
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unsigned int extra_channels,
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unsigned int parallelism)
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{
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unsigned int n_channels = parallelism;
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int vec_count;
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int n_xdp_tx;
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int n_xdp_ev;
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if (efx_separate_tx_channels)
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n_channels *= 2;
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n_channels += extra_channels;
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/* To allow XDP transmit to happen from arbitrary NAPI contexts
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* we allocate a TX queue per CPU. We share event queues across
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* multiple tx queues, assuming tx and ev queues are both
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* maximum size.
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*/
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n_xdp_tx = num_possible_cpus();
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n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_TXQ_TYPES);
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vec_count = pci_msix_vec_count(efx->pci_dev);
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if (vec_count < 0)
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return vec_count;
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max_channels = min_t(unsigned int, vec_count, max_channels);
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/* Check resources.
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* We need a channel per event queue, plus a VI per tx queue.
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* This may be more pessimistic than it needs to be.
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*/
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if (n_channels + n_xdp_ev > max_channels) {
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netif_err(efx, drv, efx->net_dev,
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"Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
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n_xdp_ev, n_channels, max_channels);
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efx->n_xdp_channels = 0;
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efx->xdp_tx_per_channel = 0;
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efx->xdp_tx_queue_count = 0;
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} else {
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efx->n_xdp_channels = n_xdp_ev;
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efx->xdp_tx_per_channel = EFX_TXQ_TYPES;
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efx->xdp_tx_queue_count = n_xdp_tx;
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n_channels += n_xdp_ev;
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netif_dbg(efx, drv, efx->net_dev,
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"Allocating %d TX and %d event queues for XDP\n",
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n_xdp_tx, n_xdp_ev);
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}
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if (vec_count < n_channels) {
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Insufficient MSI-X vectors available (%d < %u).\n",
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vec_count, n_channels);
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Performance may be reduced.\n");
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n_channels = vec_count;
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}
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n_channels = min(n_channels, max_channels);
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efx->n_channels = n_channels;
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/* Ignore XDP tx channels when creating rx channels. */
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n_channels -= efx->n_xdp_channels;
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if (efx_separate_tx_channels) {
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efx->n_tx_channels =
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min(max(n_channels / 2, 1U),
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efx->max_tx_channels);
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efx->tx_channel_offset =
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n_channels - efx->n_tx_channels;
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efx->n_rx_channels =
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max(n_channels -
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efx->n_tx_channels, 1U);
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} else {
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efx->n_tx_channels = min(n_channels, efx->max_tx_channels);
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efx->tx_channel_offset = 0;
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efx->n_rx_channels = n_channels;
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}
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efx->n_rx_channels = min(efx->n_rx_channels, parallelism);
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efx->n_tx_channels = min(efx->n_tx_channels, parallelism);
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efx->xdp_channel_offset = n_channels;
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netif_dbg(efx, drv, efx->net_dev,
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"Allocating %u RX channels\n",
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efx->n_rx_channels);
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return efx->n_channels;
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}
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/* Probe the number and type of interrupts we are able to obtain, and
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* the resulting numbers of channels and RX queues.
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*/
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int efx_probe_interrupts(struct efx_nic *efx)
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{
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unsigned int extra_channels = 0;
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unsigned int rss_spread;
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unsigned int i, j;
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int rc;
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for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
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if (efx->extra_channel_type[i])
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++extra_channels;
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if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
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unsigned int parallelism = efx_wanted_parallelism(efx);
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struct msix_entry xentries[EFX_MAX_CHANNELS];
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unsigned int n_channels;
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rc = efx_allocate_msix_channels(efx, efx->max_channels,
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extra_channels, parallelism);
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if (rc >= 0) {
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n_channels = rc;
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for (i = 0; i < n_channels; i++)
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xentries[i].entry = i;
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rc = pci_enable_msix_range(efx->pci_dev, xentries, 1,
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n_channels);
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}
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if (rc < 0) {
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/* Fall back to single channel MSI */
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netif_err(efx, drv, efx->net_dev,
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"could not enable MSI-X\n");
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if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI)
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efx->interrupt_mode = EFX_INT_MODE_MSI;
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else
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return rc;
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} else if (rc < n_channels) {
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Insufficient MSI-X vectors"
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" available (%d < %u).\n", rc, n_channels);
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netif_err(efx, drv, efx->net_dev,
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"WARNING: Performance may be reduced.\n");
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n_channels = rc;
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}
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if (rc > 0) {
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for (i = 0; i < efx->n_channels; i++)
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efx_get_channel(efx, i)->irq =
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xentries[i].vector;
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}
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}
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/* Try single interrupt MSI */
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if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
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efx->n_channels = 1;
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efx->n_rx_channels = 1;
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efx->n_tx_channels = 1;
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efx->n_xdp_channels = 0;
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efx->xdp_channel_offset = efx->n_channels;
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rc = pci_enable_msi(efx->pci_dev);
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if (rc == 0) {
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efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
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} else {
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netif_err(efx, drv, efx->net_dev,
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"could not enable MSI\n");
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if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY)
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efx->interrupt_mode = EFX_INT_MODE_LEGACY;
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else
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return rc;
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}
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}
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/* Assume legacy interrupts */
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if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
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efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
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efx->n_rx_channels = 1;
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efx->n_tx_channels = 1;
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efx->n_xdp_channels = 0;
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efx->xdp_channel_offset = efx->n_channels;
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efx->legacy_irq = efx->pci_dev->irq;
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}
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/* Assign extra channels if possible, before XDP channels */
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efx->n_extra_tx_channels = 0;
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j = efx->xdp_channel_offset;
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for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
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if (!efx->extra_channel_type[i])
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continue;
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if (j <= efx->tx_channel_offset + efx->n_tx_channels) {
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efx->extra_channel_type[i]->handle_no_channel(efx);
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} else {
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--j;
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efx_get_channel(efx, j)->type =
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efx->extra_channel_type[i];
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if (efx_channel_has_tx_queues(efx_get_channel(efx, j)))
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efx->n_extra_tx_channels++;
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}
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}
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rss_spread = efx->n_rx_channels;
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/* RSS might be usable on VFs even if it is disabled on the PF */
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#ifdef CONFIG_SFC_SRIOV
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if (efx->type->sriov_wanted) {
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efx->rss_spread = ((rss_spread > 1 ||
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!efx->type->sriov_wanted(efx)) ?
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rss_spread : efx_vf_size(efx));
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return 0;
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}
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#endif
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efx->rss_spread = rss_spread;
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return 0;
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}
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#if defined(CONFIG_SMP)
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void efx_set_interrupt_affinity(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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unsigned int cpu;
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efx_for_each_channel(channel, efx) {
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cpu = cpumask_local_spread(channel->channel,
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pcibus_to_node(efx->pci_dev->bus));
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irq_set_affinity_hint(channel->irq, cpumask_of(cpu));
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}
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}
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void efx_clear_interrupt_affinity(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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efx_for_each_channel(channel, efx)
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irq_set_affinity_hint(channel->irq, NULL);
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}
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#else
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void efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
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{
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}
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void efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
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{
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}
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#endif /* CONFIG_SMP */
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void efx_remove_interrupts(struct efx_nic *efx)
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{
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struct efx_channel *channel;
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/* Remove MSI/MSI-X interrupts */
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efx_for_each_channel(channel, efx)
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channel->irq = 0;
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pci_disable_msi(efx->pci_dev);
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pci_disable_msix(efx->pci_dev);
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/* Remove legacy interrupt */
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efx->legacy_irq = 0;
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}
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static int efx_probe_nic(struct efx_nic *efx)
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static int efx_probe_nic(struct efx_nic *efx)
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{
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{
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int rc;
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int rc;
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@ -28,6 +28,17 @@ module_param(interrupt_mode, uint, 0444);
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MODULE_PARM_DESC(interrupt_mode,
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MODULE_PARM_DESC(interrupt_mode,
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"Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
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"Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
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/* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
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* i.e. the number of CPUs among which we may distribute simultaneous
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* interrupt handling.
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*
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* Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
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* The default (0) means to assign an interrupt to each core.
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*/
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static unsigned int rss_cpus;
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module_param(rss_cpus, uint, 0444);
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MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
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static unsigned int irq_adapt_low_thresh = 8000;
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static unsigned int irq_adapt_low_thresh = 8000;
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module_param(irq_adapt_low_thresh, uint, 0644);
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module_param(irq_adapt_low_thresh, uint, 0644);
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MODULE_PARM_DESC(irq_adapt_low_thresh,
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MODULE_PARM_DESC(irq_adapt_low_thresh,
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|
|
@ -66,6 +77,317 @@ static const struct efx_channel_type efx_default_channel_type = {
|
||||||
.want_pio = true,
|
.want_pio = true,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/*************
|
||||||
|
* INTERRUPTS
|
||||||
|
*************/
|
||||||
|
|
||||||
|
static unsigned int efx_wanted_parallelism(struct efx_nic *efx)
|
||||||
|
{
|
||||||
|
cpumask_var_t thread_mask;
|
||||||
|
unsigned int count;
|
||||||
|
int cpu;
|
||||||
|
|
||||||
|
if (rss_cpus) {
|
||||||
|
count = rss_cpus;
|
||||||
|
} else {
|
||||||
|
if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) {
|
||||||
|
netif_warn(efx, probe, efx->net_dev,
|
||||||
|
"RSS disabled due to allocation failure\n");
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
count = 0;
|
||||||
|
for_each_online_cpu(cpu) {
|
||||||
|
if (!cpumask_test_cpu(cpu, thread_mask)) {
|
||||||
|
++count;
|
||||||
|
cpumask_or(thread_mask, thread_mask,
|
||||||
|
topology_sibling_cpumask(cpu));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
free_cpumask_var(thread_mask);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (count > EFX_MAX_RX_QUEUES) {
|
||||||
|
netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn,
|
||||||
|
"Reducing number of rx queues from %u to %u.\n",
|
||||||
|
count, EFX_MAX_RX_QUEUES);
|
||||||
|
count = EFX_MAX_RX_QUEUES;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If RSS is requested for the PF *and* VFs then we can't write RSS
|
||||||
|
* table entries that are inaccessible to VFs
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_SFC_SRIOV
|
||||||
|
if (efx->type->sriov_wanted) {
|
||||||
|
if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 &&
|
||||||
|
count > efx_vf_size(efx)) {
|
||||||
|
netif_warn(efx, probe, efx->net_dev,
|
||||||
|
"Reducing number of RSS channels from %u to %u for "
|
||||||
|
"VF support. Increase vf-msix-limit to use more "
|
||||||
|
"channels on the PF.\n",
|
||||||
|
count, efx_vf_size(efx));
|
||||||
|
count = efx_vf_size(efx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int efx_allocate_msix_channels(struct efx_nic *efx,
|
||||||
|
unsigned int max_channels,
|
||||||
|
unsigned int extra_channels,
|
||||||
|
unsigned int parallelism)
|
||||||
|
{
|
||||||
|
unsigned int n_channels = parallelism;
|
||||||
|
int vec_count;
|
||||||
|
int n_xdp_tx;
|
||||||
|
int n_xdp_ev;
|
||||||
|
|
||||||
|
if (efx_separate_tx_channels)
|
||||||
|
n_channels *= 2;
|
||||||
|
n_channels += extra_channels;
|
||||||
|
|
||||||
|
/* To allow XDP transmit to happen from arbitrary NAPI contexts
|
||||||
|
* we allocate a TX queue per CPU. We share event queues across
|
||||||
|
* multiple tx queues, assuming tx and ev queues are both
|
||||||
|
* maximum size.
|
||||||
|
*/
|
||||||
|
|
||||||
|
n_xdp_tx = num_possible_cpus();
|
||||||
|
n_xdp_ev = DIV_ROUND_UP(n_xdp_tx, EFX_TXQ_TYPES);
|
||||||
|
|
||||||
|
vec_count = pci_msix_vec_count(efx->pci_dev);
|
||||||
|
if (vec_count < 0)
|
||||||
|
return vec_count;
|
||||||
|
|
||||||
|
max_channels = min_t(unsigned int, vec_count, max_channels);
|
||||||
|
|
||||||
|
/* Check resources.
|
||||||
|
* We need a channel per event queue, plus a VI per tx queue.
|
||||||
|
* This may be more pessimistic than it needs to be.
|
||||||
|
*/
|
||||||
|
if (n_channels + n_xdp_ev > max_channels) {
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"Insufficient resources for %d XDP event queues (%d other channels, max %d)\n",
|
||||||
|
n_xdp_ev, n_channels, max_channels);
|
||||||
|
efx->n_xdp_channels = 0;
|
||||||
|
efx->xdp_tx_per_channel = 0;
|
||||||
|
efx->xdp_tx_queue_count = 0;
|
||||||
|
} else {
|
||||||
|
efx->n_xdp_channels = n_xdp_ev;
|
||||||
|
efx->xdp_tx_per_channel = EFX_TXQ_TYPES;
|
||||||
|
efx->xdp_tx_queue_count = n_xdp_tx;
|
||||||
|
n_channels += n_xdp_ev;
|
||||||
|
netif_dbg(efx, drv, efx->net_dev,
|
||||||
|
"Allocating %d TX and %d event queues for XDP\n",
|
||||||
|
n_xdp_tx, n_xdp_ev);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (vec_count < n_channels) {
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"WARNING: Insufficient MSI-X vectors available (%d < %u).\n",
|
||||||
|
vec_count, n_channels);
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"WARNING: Performance may be reduced.\n");
|
||||||
|
n_channels = vec_count;
|
||||||
|
}
|
||||||
|
|
||||||
|
n_channels = min(n_channels, max_channels);
|
||||||
|
|
||||||
|
efx->n_channels = n_channels;
|
||||||
|
|
||||||
|
/* Ignore XDP tx channels when creating rx channels. */
|
||||||
|
n_channels -= efx->n_xdp_channels;
|
||||||
|
|
||||||
|
if (efx_separate_tx_channels) {
|
||||||
|
efx->n_tx_channels =
|
||||||
|
min(max(n_channels / 2, 1U),
|
||||||
|
efx->max_tx_channels);
|
||||||
|
efx->tx_channel_offset =
|
||||||
|
n_channels - efx->n_tx_channels;
|
||||||
|
efx->n_rx_channels =
|
||||||
|
max(n_channels -
|
||||||
|
efx->n_tx_channels, 1U);
|
||||||
|
} else {
|
||||||
|
efx->n_tx_channels = min(n_channels, efx->max_tx_channels);
|
||||||
|
efx->tx_channel_offset = 0;
|
||||||
|
efx->n_rx_channels = n_channels;
|
||||||
|
}
|
||||||
|
|
||||||
|
efx->n_rx_channels = min(efx->n_rx_channels, parallelism);
|
||||||
|
efx->n_tx_channels = min(efx->n_tx_channels, parallelism);
|
||||||
|
|
||||||
|
efx->xdp_channel_offset = n_channels;
|
||||||
|
|
||||||
|
netif_dbg(efx, drv, efx->net_dev,
|
||||||
|
"Allocating %u RX channels\n",
|
||||||
|
efx->n_rx_channels);
|
||||||
|
|
||||||
|
return efx->n_channels;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Probe the number and type of interrupts we are able to obtain, and
|
||||||
|
* the resulting numbers of channels and RX queues.
|
||||||
|
*/
|
||||||
|
int efx_probe_interrupts(struct efx_nic *efx)
|
||||||
|
{
|
||||||
|
unsigned int extra_channels = 0;
|
||||||
|
unsigned int rss_spread;
|
||||||
|
unsigned int i, j;
|
||||||
|
int rc;
|
||||||
|
|
||||||
|
for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++)
|
||||||
|
if (efx->extra_channel_type[i])
|
||||||
|
++extra_channels;
|
||||||
|
|
||||||
|
if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
|
||||||
|
unsigned int parallelism = efx_wanted_parallelism(efx);
|
||||||
|
struct msix_entry xentries[EFX_MAX_CHANNELS];
|
||||||
|
unsigned int n_channels;
|
||||||
|
|
||||||
|
rc = efx_allocate_msix_channels(efx, efx->max_channels,
|
||||||
|
extra_channels, parallelism);
|
||||||
|
if (rc >= 0) {
|
||||||
|
n_channels = rc;
|
||||||
|
for (i = 0; i < n_channels; i++)
|
||||||
|
xentries[i].entry = i;
|
||||||
|
rc = pci_enable_msix_range(efx->pci_dev, xentries, 1,
|
||||||
|
n_channels);
|
||||||
|
}
|
||||||
|
if (rc < 0) {
|
||||||
|
/* Fall back to single channel MSI */
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"could not enable MSI-X\n");
|
||||||
|
if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI)
|
||||||
|
efx->interrupt_mode = EFX_INT_MODE_MSI;
|
||||||
|
else
|
||||||
|
return rc;
|
||||||
|
} else if (rc < n_channels) {
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"WARNING: Insufficient MSI-X vectors"
|
||||||
|
" available (%d < %u).\n", rc, n_channels);
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"WARNING: Performance may be reduced.\n");
|
||||||
|
n_channels = rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (rc > 0) {
|
||||||
|
for (i = 0; i < efx->n_channels; i++)
|
||||||
|
efx_get_channel(efx, i)->irq =
|
||||||
|
xentries[i].vector;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Try single interrupt MSI */
|
||||||
|
if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
|
||||||
|
efx->n_channels = 1;
|
||||||
|
efx->n_rx_channels = 1;
|
||||||
|
efx->n_tx_channels = 1;
|
||||||
|
efx->n_xdp_channels = 0;
|
||||||
|
efx->xdp_channel_offset = efx->n_channels;
|
||||||
|
rc = pci_enable_msi(efx->pci_dev);
|
||||||
|
if (rc == 0) {
|
||||||
|
efx_get_channel(efx, 0)->irq = efx->pci_dev->irq;
|
||||||
|
} else {
|
||||||
|
netif_err(efx, drv, efx->net_dev,
|
||||||
|
"could not enable MSI\n");
|
||||||
|
if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY)
|
||||||
|
efx->interrupt_mode = EFX_INT_MODE_LEGACY;
|
||||||
|
else
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Assume legacy interrupts */
|
||||||
|
if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
|
||||||
|
efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0);
|
||||||
|
efx->n_rx_channels = 1;
|
||||||
|
efx->n_tx_channels = 1;
|
||||||
|
efx->n_xdp_channels = 0;
|
||||||
|
efx->xdp_channel_offset = efx->n_channels;
|
||||||
|
efx->legacy_irq = efx->pci_dev->irq;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Assign extra channels if possible, before XDP channels */
|
||||||
|
efx->n_extra_tx_channels = 0;
|
||||||
|
j = efx->xdp_channel_offset;
|
||||||
|
for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) {
|
||||||
|
if (!efx->extra_channel_type[i])
|
||||||
|
continue;
|
||||||
|
if (j <= efx->tx_channel_offset + efx->n_tx_channels) {
|
||||||
|
efx->extra_channel_type[i]->handle_no_channel(efx);
|
||||||
|
} else {
|
||||||
|
--j;
|
||||||
|
efx_get_channel(efx, j)->type =
|
||||||
|
efx->extra_channel_type[i];
|
||||||
|
if (efx_channel_has_tx_queues(efx_get_channel(efx, j)))
|
||||||
|
efx->n_extra_tx_channels++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
rss_spread = efx->n_rx_channels;
|
||||||
|
/* RSS might be usable on VFs even if it is disabled on the PF */
|
||||||
|
#ifdef CONFIG_SFC_SRIOV
|
||||||
|
if (efx->type->sriov_wanted) {
|
||||||
|
efx->rss_spread = ((rss_spread > 1 ||
|
||||||
|
!efx->type->sriov_wanted(efx)) ?
|
||||||
|
rss_spread : efx_vf_size(efx));
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
efx->rss_spread = rss_spread;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SMP)
|
||||||
|
void efx_set_interrupt_affinity(struct efx_nic *efx)
|
||||||
|
{
|
||||||
|
struct efx_channel *channel;
|
||||||
|
unsigned int cpu;
|
||||||
|
|
||||||
|
efx_for_each_channel(channel, efx) {
|
||||||
|
cpu = cpumask_local_spread(channel->channel,
|
||||||
|
pcibus_to_node(efx->pci_dev->bus));
|
||||||
|
irq_set_affinity_hint(channel->irq, cpumask_of(cpu));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void efx_clear_interrupt_affinity(struct efx_nic *efx)
|
||||||
|
{
|
||||||
|
struct efx_channel *channel;
|
||||||
|
|
||||||
|
efx_for_each_channel(channel, efx)
|
||||||
|
irq_set_affinity_hint(channel->irq, NULL);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
void
|
||||||
|
efx_set_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
efx_clear_interrupt_affinity(struct efx_nic *efx __attribute__ ((unused)))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_SMP */
|
||||||
|
|
||||||
|
void efx_remove_interrupts(struct efx_nic *efx)
|
||||||
|
{
|
||||||
|
struct efx_channel *channel;
|
||||||
|
|
||||||
|
/* Remove MSI/MSI-X interrupts */
|
||||||
|
efx_for_each_channel(channel, efx)
|
||||||
|
channel->irq = 0;
|
||||||
|
pci_disable_msi(efx->pci_dev);
|
||||||
|
pci_disable_msix(efx->pci_dev);
|
||||||
|
|
||||||
|
/* Remove legacy interrupt */
|
||||||
|
efx->legacy_irq = 0;
|
||||||
|
}
|
||||||
|
|
||||||
/**************************************************************************
|
/**************************************************************************
|
||||||
*
|
*
|
||||||
* Channel handling
|
* Channel handling
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue