mirror of https://gitee.com/openkylin/linux.git
drm/i915: Populate pipe_offsets[] & co. accurately
At some point people have started to assume that pipe_offsets[] & co. are only populated for pipes and whatnot that actually exist. That is in fact not currently true, but we can easily make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190305192905.7140-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Ville Syrjälä
parent
171d156257
commit
37fbbd4905
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@ -35,7 +35,37 @@
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#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
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#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
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#define GEN_DEFAULT_PIPEOFFSETS \
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#define I845_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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}
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#define I9XX_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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}
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#define IVB_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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[TRANSCODER_C] = PIPE_C_OFFSET, \
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}, \
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.trans_offsets = { \
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[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
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[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
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}
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#define HSW_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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@ -49,7 +79,7 @@
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[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
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}
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#define GEN_CHV_PIPEOFFSETS \
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#define CHV_PIPE_OFFSETS \
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.pipe_offsets = { \
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[TRANSCODER_A] = PIPE_A_OFFSET, \
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[TRANSCODER_B] = PIPE_B_OFFSET, \
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@ -61,11 +91,30 @@
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[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
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}
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#define CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
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#define I845_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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}
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#define I9XX_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = CURSOR_B_OFFSET, \
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}
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#define CHV_CURSOR_OFFSETS \
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = CURSOR_B_OFFSET, \
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[PIPE_C] = CHV_CURSOR_C_OFFSET, \
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}
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#define IVB_CURSOR_OFFSETS \
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.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
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.cursor_offsets = { \
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[PIPE_A] = CURSOR_A_OFFSET, \
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[PIPE_B] = IVB_CURSOR_B_OFFSET, \
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[PIPE_C] = IVB_CURSOR_C_OFFSET, \
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}
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#define BDW_COLORS \
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.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
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@ -85,7 +134,25 @@
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#define GEN_DEFAULT_PAGE_SIZES \
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.page_sizes = I915_GTT_PAGE_SIZE_4K
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#define GEN2_FEATURES \
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#define I830_FEATURES \
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GEN(2), \
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.is_mobile = 1, \
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.num_pipes = 2, \
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.display.has_overlay = 1, \
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.display.cursor_needs_physical = 1, \
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.display.overlay_needs_physical = 1, \
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.display.has_gmch = 1, \
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.gpu_reset_clobbers_display = true, \
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.hws_needs_physical = 1, \
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.unfenced_needs_alignment = 1, \
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = false, \
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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#define I845_FEATURES \
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GEN(2), \
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.num_pipes = 1, \
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.display.has_overlay = 1, \
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@ -97,34 +164,28 @@
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = false, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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CURSOR_OFFSETS
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I845_PIPE_OFFSETS, \
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I845_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i830_info = {
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GEN2_FEATURES,
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I830_FEATURES,
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PLATFORM(INTEL_I830),
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.is_mobile = 1,
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.display.cursor_needs_physical = 1,
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.num_pipes = 2, /* legal, last one wins */
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};
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static const struct intel_device_info intel_i845g_info = {
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GEN2_FEATURES,
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I845_FEATURES,
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PLATFORM(INTEL_I845G),
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};
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static const struct intel_device_info intel_i85x_info = {
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GEN2_FEATURES,
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I830_FEATURES,
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PLATFORM(INTEL_I85X),
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.is_mobile = 1,
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.num_pipes = 2, /* legal, last one wins */
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.display.cursor_needs_physical = 1,
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.display.has_fbc = 1,
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};
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static const struct intel_device_info intel_i865g_info = {
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GEN2_FEATURES,
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I845_FEATURES,
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PLATFORM(INTEL_I865G),
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};
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@ -136,9 +197,9 @@ static const struct intel_device_info intel_i865g_info = {
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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CURSOR_OFFSETS
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i915g_info = {
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GEN3_FEATURES,
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@ -213,9 +274,9 @@ static const struct intel_device_info intel_pineview_info = {
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.engine_mask = BIT(RCS0), \
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.has_snoop = true, \
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.has_coherent_ggtt = true, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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CURSOR_OFFSETS
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_i965g_info = {
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GEN4_FEATURES,
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@ -262,9 +323,9 @@ static const struct intel_device_info intel_gm45_info = {
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.has_coherent_ggtt = true, \
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/* ilk does support rc6, but we do not implement [power] contexts */ \
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.has_rc6 = 0, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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CURSOR_OFFSETS
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_ironlake_d_info = {
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GEN5_FEATURES,
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@ -289,9 +350,9 @@ static const struct intel_device_info intel_ironlake_m_info = {
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.ppgtt = INTEL_PPGTT_ALIASING, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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CURSOR_OFFSETS
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I9XX_PIPE_OFFSETS, \
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I9XX_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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#define SNB_D_PLATFORM \
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GEN6_FEATURES, \
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@ -334,9 +395,9 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
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.has_rc6 = 1, \
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.has_rc6p = 1, \
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.ppgtt = INTEL_PPGTT_FULL, \
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GEN_DEFAULT_PIPEOFFSETS, \
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GEN_DEFAULT_PAGE_SIZES, \
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IVB_CURSOR_OFFSETS
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IVB_PIPE_OFFSETS, \
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IVB_CURSOR_OFFSETS, \
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GEN_DEFAULT_PAGE_SIZES
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#define IVB_D_PLATFORM \
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GEN7_FEATURES, \
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@ -391,9 +452,9 @@ static const struct intel_device_info intel_valleyview_info = {
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.has_coherent_ggtt = false,
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.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
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.display_mmio_offset = VLV_DISPLAY_BASE,
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I9XX_PIPE_OFFSETS,
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I9XX_CURSOR_OFFSETS,
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GEN_DEFAULT_PAGE_SIZES,
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GEN_DEFAULT_PIPEOFFSETS,
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CURSOR_OFFSETS
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};
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#define G75_FEATURES \
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@ -404,6 +465,7 @@ static const struct intel_device_info intel_valleyview_info = {
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.display.has_psr = 1, \
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.display.has_dp_mst = 1, \
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.has_rc6p = 0 /* RC6p removed-by HSW */, \
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HSW_PIPE_OFFSETS, \
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.has_runtime_pm = 1
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#define HSW_PLATFORM \
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@ -483,10 +545,10 @@ static const struct intel_device_info intel_cherryview_info = {
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.has_snoop = true,
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.has_coherent_ggtt = false,
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.display_mmio_offset = VLV_DISPLAY_BASE,
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GEN_DEFAULT_PAGE_SIZES,
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GEN_CHV_PIPEOFFSETS,
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CURSOR_OFFSETS,
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CHV_PIPE_OFFSETS,
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CHV_CURSOR_OFFSETS,
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CHV_COLORS,
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GEN_DEFAULT_PAGE_SIZES,
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};
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#define GEN9_DEFAULT_PAGE_SIZES \
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@ -559,10 +621,10 @@ static const struct intel_device_info intel_skylake_gt4_info = {
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.has_snoop = true, \
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.has_coherent_ggtt = false, \
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.display.has_ipc = 1, \
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GEN9_DEFAULT_PAGE_SIZES, \
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GEN_DEFAULT_PIPEOFFSETS, \
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HSW_PIPE_OFFSETS, \
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IVB_CURSOR_OFFSETS, \
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BDW_COLORS
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BDW_COLORS, \
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GEN9_DEFAULT_PAGE_SIZES
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static const struct intel_device_info intel_broxton_info = {
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GEN9_LP_FEATURES,
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