From 382fb77891b6f9b067fc801cc63503d0d1d07dfb Mon Sep 17 00:00:00 2001 From: hersen wu Date: Wed, 29 May 2019 23:28:55 -0500 Subject: [PATCH] drm/amd/powerplay: allow dc request uclk change when dc set mode or color format in frame buffer change, it may request clock changes, like dispclk, dcfclk, uclk. after smu get clock requests, smu will make decision. Signed-off-by: hersen wu Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index e77cfb96fc56..bab61fe46b46 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1275,7 +1275,8 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, if (!smu->pm_enabled) return -EINVAL; - if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || + smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { switch (clk_type) { case amd_pp_dcef_clock: clk_select = SMU_DCEFCLK; @@ -1289,6 +1290,9 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, case amd_pp_phy_clock: clk_select = SMU_PHYCLK; break; + case amd_pp_mem_clock: + clk_select = SMU_UCLK; + break; default: pr_info("[%s] Invalid Clock Type!", __func__); ret = -EINVAL; @@ -1298,8 +1302,10 @@ smu_v11_0_display_clock_voltage_request(struct smu_context *smu, if (ret) goto failed; + mutex_lock(&smu->mutex); ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, (smu_clk_get_index(smu, clk_select) << 16) | clk_freq); + mutex_unlock(&smu->mutex); } failed: