mirror of https://gitee.com/openkylin/linux.git
Pin control fixes for the v5.12 kernel cycle:
- Fix up some Intel GPIO base calculations.
- Fix a register offset in the Microchip driver.
- Fix suspend/resume bug in the Rockchip driver.
- Default pull up strength in the Qualcomm LPASS
driver.
- Fix two pingroup offsets in the Qualcomm SC7280
driver.
- Fix SDC1 register offset in the Qualcomm SC7280
driver.
- Fix a nasty string concatenation in the
Qualcomm SDX55 driver.
- Check the REVID register to see if the device is
real or virtualized during virtualization in the
Intel driver.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmBkalgACgkQQRCzN7AZ
XXMY/g/+OUZm+mT0DR0AFDW7UkMytns0Zgt7Zk9V6W5rytW7731LNCC5CRF1F3kI
iZiutqNfe7uDWop5yo1ub8UqCxBtgrJADzXT4uTGid11jQrsfwUjZEqjlW1J4oHz
Y4cfmLCPtuB4rA1GrISqYQ2s2YO2+kdFVdL8ZrhFQug5GEOJrtmjAYvTU1GshaLH
9oxd7bg5QV2ZmzAQoH7tScqUi+60u7CqWLBJzuW6/qIBCBpYxc6NFLlfPbuqJbyb
NuJeRl+e7OA2tQE5CR4ymQyuoz7iGCrgsDIOi7maADDTJQEW/RPG9565qzqQxCgv
UFt1sqodgegEgXLRNJG6Y9zO1qktCzDHJGNFyH9EZ2FHVKox+Gicf8TxYM3ulHca
az/qs+MXH32YdLr//lg6XvogAMjnl3nXeq9j1U7nunki4N93oxBhq89d5qBcyZSP
/3D53HViq6EEcBnChAZ64SY21Ro7HNzE6x5bOSL2HPsWy9B8U5jRgAkHxPjd8/Vr
LF5EPblI+bZc8fOxAi9ifMu9OROB+I5ZUm00zYzucJUKoMtrkAkObW9/GS88vpwN
j6uAAr/WFlWaXpKynIxyME3zPuhoyZHFlSnI8LI3UTBiZtFsxoMWbVP1OVkbK6bc
kUtQUPsE0T4OowYa+ulYet+US/LucmVn7KgTFGOodSKtpxHU7Mk=
=+Gsn
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
"Some overly ripe fixes for the v5.12 kernel. I should have sent
earlier but had my head stuck in GDB.
All are driver fixes:
- Fix up some Intel GPIO base calculations.
- Fix a register offset in the Microchip driver.
- Fix suspend/resume bug in the Rockchip driver.
- Default pull up strength in the Qualcomm LPASS driver.
- Fix two pingroup offsets in the Qualcomm SC7280 driver.
- Fix SDC1 register offset in the Qualcomm SC7280 driver.
- Fix a nasty string concatenation in the Qualcomm SDX55 driver.
- Check the REVID register to see if the device is real or
virtualized during virtualization in the Intel driver"
* tag 'pinctrl-v5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: intel: check REVID register value for device presence
pinctrl: qcom: fix unintentional string concatenation
pinctrl: qcom: sc7280: Fix SDC1_RCLK configurations
pinctrl: qcom: sc7280: Fix SDC_QDSD_PINGROUP and UFS_RESET offsets
pinctrl: qcom: lpass lpi: use default pullup/strength values
pinctrl: rockchip: fix restore error in resume
pinctrl: microchip-sgpio: Fix wrong register offset for IRQ trigger
pinctrl: intel: Show the GPIO base calculation explicitly
This commit is contained in:
Linus Torvalds
commit
39192106d4
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@ -1357,6 +1357,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
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gpps[i].gpio_base = 0;
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break;
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case INTEL_GPIO_BASE_NOMAP:
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break;
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default:
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break;
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}
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@ -1393,6 +1394,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
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gpps[i].size = min(gpp_size, npins);
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npins -= gpps[i].size;
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gpps[i].gpio_base = gpps[i].base;
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gpps[i].padown_num = padown_num;
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/*
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@ -1491,8 +1493,13 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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/* Determine community features based on the revision */
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/*
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* Determine community features based on the revision.
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* A value of all ones means the device is not present.
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*/
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value = readl(regs + REVID);
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if (value == ~0u)
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return -ENODEV;
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if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
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community->features |= PINCTRL_FEATURE_DEBOUNCE;
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community->features |= PINCTRL_FEATURE_1K_PD;
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@ -572,7 +572,7 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
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/* Type value spread over 2 registers sets: low, high bit */
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sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
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BIT(addr.port), (!!(type & 0x1)) << addr.port);
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sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
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sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
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BIT(addr.port), (!!(type & 0x2)) << addr.port);
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if (type == SGPIO_INT_TRG_LEVEL)
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@ -3727,12 +3727,15 @@ static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
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static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
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{
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struct rockchip_pinctrl *info = dev_get_drvdata(dev);
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int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
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rk3288_grf_gpio6c_iomux |
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GPIO6C6_SEL_WRITE_ENABLE);
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int ret;
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if (ret)
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return ret;
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if (info->ctrl->type == RK3288) {
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ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
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rk3288_grf_gpio6c_iomux |
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GPIO6C6_SEL_WRITE_ENABLE);
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if (ret)
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return ret;
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}
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return pinctrl_force_default(info->pctl_dev);
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}
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@ -392,7 +392,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
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unsigned long *configs, unsigned int nconfs)
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{
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struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
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unsigned int param, arg, pullup, strength;
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unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
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bool value, output_enabled = false;
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const struct lpi_pingroup *g;
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unsigned long sval;
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@ -1439,14 +1439,14 @@ static const struct msm_pingroup sc7280_groups[] = {
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[172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _),
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[173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
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[174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
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[175] = UFS_RESET(ufs_reset, 0x1be000),
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[176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
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[177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
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[178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
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[179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
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[180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
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[181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
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[182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
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[175] = UFS_RESET(ufs_reset, 0xbe000),
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[176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6),
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[177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6),
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[178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3),
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[179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0),
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[180] = SDC_QDSD_PINGROUP(sdc2_clk, 0xb4000, 14, 6),
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[181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xb4000, 11, 3),
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[182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0),
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};
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static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
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@ -423,7 +423,7 @@ static const char * const gpio_groups[] = {
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static const char * const qdss_stm_groups[] = {
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"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13",
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"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22",
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"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
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"gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62",
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"gpio63", "gpio64", "gpio65", "gpio66",
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};
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