mirror of https://gitee.com/openkylin/linux.git
xhci: support new USB 3.1 hub request to get extended port status
USB 3.1 adds different types of Get Port Status request. The Get Extended Port Status request returns 4 additional bytes after the normal portstatus and portchange words containing link speed and lane information about a connected enhanced super speed device Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -659,6 +659,22 @@ static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
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}
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}
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static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
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{
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u32 ext_stat = 0;
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int speed_id;
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/* only support rx and tx lane counts of 1 in usb3.1 spec */
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speed_id = DEV_PORT_SPEED(raw_port_status);
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ext_stat |= speed_id; /* bits 3:0, RX speed id */
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ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
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ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
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ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
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return ext_stat;
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}
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/*
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* Converts a raw xHCI port status into the format that external USB 2.0 or USB
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* 3.0 hubs use.
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@ -874,6 +890,19 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
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xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
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put_unaligned(cpu_to_le32(status), (__le32 *) buf);
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/* if USB 3.1 extended port status return additional 4 bytes */
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if (wValue == 0x02) {
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u32 port_li;
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if (hcd->speed < HCD_USB31 || wLength != 8) {
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xhci_err(xhci, "get ext port status invalid parameter\n");
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retval = -EINVAL;
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break;
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}
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port_li = readl(port_array[wIndex] + PORTLI);
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status = xhci_get_ext_port_status(temp, port_li);
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put_unaligned_le32(cpu_to_le32(status), &buf[4]);
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}
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break;
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case SetPortFeature:
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if (wValue == USB_PORT_FEAT_LINK_STATE)
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@ -335,6 +335,7 @@ struct xhci_op_regs {
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#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
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#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
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#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
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#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
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/* Bits 20:23 in the Slot Context are the speed for the device */
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#define SLOT_SPEED_FS (XDEV_FS << 10)
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@ -419,6 +420,9 @@ struct xhci_op_regs {
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#define PORT_L1DS(p) (((p) & 0xff) << 8)
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#define PORT_HLE (1 << 16)
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/* USB3 Protocol PORTLI Port Link Information */
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#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
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#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
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/* USB2 Protocol PORTHLPMC */
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#define PORT_HIRDM(p)((p) & 3)
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