mirror of https://gitee.com/openkylin/linux.git
arm64: dts: renesas: r8a77961: Add SCIF and HSCIF nodes
Add the device nodes for all SCIF and HSCIF serial ports on R-Car M3-W+. Add the missing DMA properties to the already-present SCIF2 node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
This commit is contained in:
Geert Uytterhoeven
parent
8ab47ffc8d
commit
3971a77348
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@ -626,10 +626,92 @@ i2c_dvfs: i2c@e60b0000 {
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status = "disabled";
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status = "disabled";
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};
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};
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hscif0: serial@e6540000 {
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compatible = "renesas,hscif-r8a77961",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6540000 0 0x60>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 520>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x31>, <&dmac1 0x30>,
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<&dmac2 0x31>, <&dmac2 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 520>;
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status = "disabled";
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};
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hscif1: serial@e6550000 {
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hscif1: serial@e6550000 {
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compatible = "renesas,hscif-r8a77961",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6550000 0 0x60>;
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reg = <0 0xe6550000 0 0x60>;
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/* placeholder */
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 519>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x33>, <&dmac1 0x32>,
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<&dmac2 0x33>, <&dmac2 0x32>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 519>;
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status = "disabled";
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};
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hscif2: serial@e6560000 {
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compatible = "renesas,hscif-r8a77961",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6560000 0 0x60>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 518>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x35>, <&dmac1 0x34>,
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<&dmac2 0x35>, <&dmac2 0x34>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 518>;
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status = "disabled";
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};
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hscif3: serial@e66a0000 {
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compatible = "renesas,hscif-r8a77961",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe66a0000 0 0x60>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 517>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x37>, <&dmac0 0x36>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 517>;
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status = "disabled";
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};
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hscif4: serial@e66b0000 {
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compatible = "renesas,hscif-r8a77961",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe66b0000 0 0x60>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 516>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x39>, <&dmac0 0x38>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 516>;
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status = "disabled";
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};
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};
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hsusb: usb@e6590000 {
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hsusb: usb@e6590000 {
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@ -852,9 +934,38 @@ pwm1: pwm@e6e31000 {
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/* placeholder */
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/* placeholder */
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};
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a77961",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 207>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x51>, <&dmac1 0x50>,
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<&dmac2 0x51>, <&dmac2 0x50>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 207>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a77961",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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reg = <0 0xe6e68000 0 64>;
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/* placeholder */
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 206>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x53>, <&dmac1 0x52>,
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<&dmac2 0x53>, <&dmac2 0x52>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 206>;
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status = "disabled";
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};
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};
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scif2: serial@e6e88000 {
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scif2: serial@e6e88000 {
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@ -866,11 +977,63 @@ scif2: serial@e6e88000 {
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>,
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<&dmac2 0x13>, <&dmac2 0x12>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 310>;
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resets = <&cpg 310>;
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status = "disabled";
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status = "disabled";
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};
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};
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scif3: serial@e6c50000 {
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compatible = "renesas,scif-r8a77961",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6c50000 0 64>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 204>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x57>, <&dmac0 0x56>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 204>;
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status = "disabled";
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};
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scif4: serial@e6c40000 {
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compatible = "renesas,scif-r8a77961",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6c40000 0 64>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 203>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x59>, <&dmac0 0x58>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 203>;
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status = "disabled";
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};
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scif5: serial@e6f30000 {
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compatible = "renesas,scif-r8a77961",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6f30000 0 64>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 202>,
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<&cpg CPG_CORE R8A77961_CLK_S3D1>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
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<&dmac2 0x5b>, <&dmac2 0x5a>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
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resets = <&cpg 202>;
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status = "disabled";
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};
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vin0: video@e6ef0000 {
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vin0: video@e6ef0000 {
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reg = <0 0xe6ef0000 0 0x1000>;
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reg = <0 0xe6ef0000 0 0x1000>;
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/* placeholder */
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/* placeholder */
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