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ARM: dts: imx6: add mmdc ipg clock 

i.MX6 SoCs has MMDC clock gates in CCM CCGR, add
clock property for MMDC driver's clock operation.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Anson Huang 2018-08-31 15:53:18 +08:00 committed by Shawn Guo
parent 46f3b54de8
commit 39db0e136b
5 changed files with 5 additions and 0 deletions
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1
arch/arm/boot/dts/imx6qdl.dtsi
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@ -1115,6 +1115,7 @@ romcp@21ac000 {
mmdc0: mmdc@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
};
mmdc1: mmdc@21b4000 { /* MMDC1 */

1
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -921,6 +921,7 @@ i2c3: i2c@21a8000 {
mmdc: mmdc@21b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
};
rngb: rngb@21b4000 {

1
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -770,6 +770,7 @@ i2c3: i2c@21a8000 {
mmdc: memory-controller@21b0000 {
compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
};
ocotp: ocotp-ctrl@21bc000 {

1
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -1002,6 +1002,7 @@ i2c3: i2c@21a8000 {
mmdc: mmdc@21b0000 {
compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
};
fec2: ethernet@21b4000 {

1
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -917,6 +917,7 @@ i2c3: i2c@21a8000 {
mmdc: mmdc@21b0000 {
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
};
weim: weim@21b8000 {