mirror of https://gitee.com/openkylin/linux.git
rtlwifi: remove duplicate declarations and macros in headers
This patch brings no functional change. There are still duplicate macros across the rtlwifi directory, for example IQK_DELAY_TIME is defined multiple times, sometimes with different values, this patch only removes duplicates within the same header file. Signed-off-by: Catalin Iacob <iacobcatalin@gmail.com> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -114,7 +114,6 @@ void rtl_init_rfkill(struct ieee80211_hw *hw);
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void rtl_deinit_rfkill(struct ieee80211_hw *hw);
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void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
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void rtl_watch_dog_timer_callback(unsigned long data);
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void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
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bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
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@ -39,9 +39,7 @@
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#define RT_CANNOT_IO(hw) false
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#define HIGHPOWER_RADIOA_ARRAYLEN 22
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#define IQK_ADDA_REG_NUM 16
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1
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#define APK_BB_REG_NUM 5
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#define APK_AFE_REG_NUM 16
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@ -152,8 +152,6 @@ enum version_8192c {
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#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
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((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
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#define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
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#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \
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((GET_CVID_CUT_VERSION(version)) ? false : true) : false)
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#define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
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#define IS_CHIP_VENDOR_UMC(version) \
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((version & CHIP_VENDOR_UMC) ? true : false)
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@ -39,9 +39,7 @@
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#define RT_CANNOT_IO(hw) false
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#define HIGHPOWER_RADIOA_ARRAYLEN 22
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#define IQK_ADDA_REG_NUM 16
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1
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#define APK_BB_REG_NUM 5
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#define APK_AFE_REG_NUM 16
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@ -226,7 +224,6 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
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enum radio_path rfpath);
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bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
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u32 rfpath);
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bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
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bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
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enum rf_pwrstate rfpwr_state);
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void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
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@ -560,7 +560,6 @@
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#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
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#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
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#define EEPROM_DEFAULT_HT20_DIFF 2
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#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
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#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
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#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
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@ -639,17 +638,8 @@
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#define EEPROM_TXPWR_GROUP 0x6F
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#define EEPROM_TSSI_A 0x76
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#define EEPROM_TSSI_B 0x77
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#define EEPROM_THERMAL_METER 0x78
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#define EEPROM_CHANNELPLAN 0x75
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#define RF_OPTION1 0x79
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#define RF_OPTION2 0x7A
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#define RF_OPTION3 0x7B
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#define RF_OPTION4 0x7C
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#define STOPBECON BIT(6)
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#define STOPHIGHT BIT(5)
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#define STOPMGT BIT(4)
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@ -689,13 +679,6 @@
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#define RSV_CTRL 0x001C
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#define RD_CTRL 0x0524
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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#define REG_USB_AGG_TO 0xFE5C
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#define REG_USB_AGG_TH 0xFE5D
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#define REG_USB_VID 0xFE60
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#define REG_USB_PID 0xFE62
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#define REG_USB_OPTIONAL 0xFE64
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@ -1196,9 +1179,6 @@
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#define POLLING_LLT_THRESHOLD 20
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#define POLLING_READY_TIMEOUT_COUNT 1000
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#define MAX_MSS_DENSITY_2T 0x13
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#define MAX_MSS_DENSITY_1T 0x0A
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#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
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#define EPROM_CMD_CONFIG 0x3
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#define EPROM_CMD_LOAD 1
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@ -39,9 +39,7 @@
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#define RT_CANNOT_IO(hw) false
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#define HIGHPOWER_RADIOA_ARRAYLEN 22
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#define IQK_ADDA_REG_NUM 16
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#define MAX_TOLERANCE 5
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#define IQK_DELAY_TIME 1
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#define APK_BB_REG_NUM 5
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#define APK_AFE_REG_NUM 16
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@ -173,6 +171,5 @@ void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
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unsigned long *flag);
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u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
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void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
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void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
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#endif
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@ -425,14 +425,9 @@
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#define EXT_IMEM_CODE_DONE BIT(2)
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#define IMEM_CHK_RPT BIT(1)
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#define IMEM_CODE_DONE BIT(0)
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#define IMEM_CODE_DONE BIT(0)
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#define IMEM_CHK_RPT BIT(1)
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#define EMEM_CODE_DONE BIT(2)
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#define EMEM_CHK_RPT BIT(3)
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#define DMEM_CODE_DONE BIT(4)
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#define IMEM_RDY BIT(5)
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#define BASECHG BIT(6)
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#define FWRDY BIT(7)
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#define LOAD_FW_READY (IMEM_CODE_DONE | \
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IMEM_CHK_RPT | \
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EMEM_CODE_DONE | \
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@ -192,8 +192,6 @@ enum hardware_type {
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(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
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#define IS_HARDWARE_TYPE_8723(rtlhal) \
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(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
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#define IS_HARDWARE_TYPE_8723U(rtlhal) \
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(rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
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#define RX_HAL_IS_CCK_RATE(_pdesc)\
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(_pdesc->rxmcs == DESC92_RATE1M || \
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