mirror of https://gitee.com/openkylin/linux.git
sh: SH-2007 board support.
This patch series adds support for ITO Co., Ltd.'s SH-2007 reference platform (A PC-104 based SH7780 platform). This is a direct port of the out-of-tree board support from the vendor's kernel, originally located at: http://ms-n.org/sh-linux/kernel/ More information on the board and the vendor can be obtained from the vendor's site at: http://www.itonet.co.jp/ Presently supported peripherals are CF and ethernet, with support for the on-board IDE still pending further testing. Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Hitoshi Mitake
Paul Mundt
parent
dcac0d9827
commit
3a59826443
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@ -309,6 +309,17 @@ config SH_POLARIS
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help
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Select if configuring for an SMSC Polaris development board
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config SH_SH2007
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bool "SH-2007 board"
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select NO_IOPORT
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depends on CPU_SUBTYPE_SH7780
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help
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SH-2007 is a single-board computer based around SH7780 chip
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intended for embedded applications.
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It has an Ethernet interface (SMC9118), direct connected
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Compact Flash socket, two serial ports and PC-104 bus.
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More information at <http://sh2000.sh-linux.org>.
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endmenu
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source "arch/sh/boards/mach-r2d/Kconfig"
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@ -2,6 +2,7 @@
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# Specific board support, not covered by a mach group.
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#
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obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
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obj-$(CONFIG_SH_SH2007) += board-sh2007.o
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obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
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obj-$(CONFIG_SH_URQUELL) += board-urquell.o
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obj-$(CONFIG_SH_SHMIN) += board-shmin.o
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@ -0,0 +1,133 @@
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/*
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* SH-2007 board support.
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*
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* Copyright (C) 2003, 2004 SUGIOKA Toshinobu
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* Copyright (C) 2010 Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp>
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/smsc911x.h>
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#include <linux/platform_device.h>
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#include <linux/ata_platform.h>
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#include <linux/io.h>
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#include <asm/machvec.h>
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#include <mach/sh2007.h>
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struct smsc911x_platform_config smc911x_info = {
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.flags = SMSC911X_USE_32BIT,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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};
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static struct resource smsc9118_0_resources[] = {
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[0] = {
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.start = SMC0_BASE,
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.end = SMC0_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x240),
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.end = evt2irq(0x240),
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct resource smsc9118_1_resources[] = {
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[0] = {
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.start = SMC1_BASE,
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.end = SMC1_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x280),
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.end = evt2irq(0x280),
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device smsc9118_0_device = {
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.name = "smsc911x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smsc9118_0_resources),
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.resource = smsc9118_0_resources,
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.dev = {
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.platform_data = &smc911x_info,
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},
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};
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static struct platform_device smsc9118_1_device = {
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.name = "smsc911x",
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.id = 1,
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.num_resources = ARRAY_SIZE(smsc9118_1_resources),
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.resource = smsc9118_1_resources,
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.dev = {
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.platform_data = &smc911x_info,
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},
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};
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static struct resource cf_resources[] = {
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[0] = {
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.start = CF_BASE + CF_OFFSET,
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.end = CF_BASE + CF_OFFSET + 0x0f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CF_BASE + CF_OFFSET + 0x206,
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.end = CF_BASE + CF_OFFSET + 0x20f,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = evt2irq(0x2c0),
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.end = evt2irq(0x2c0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cf_device = {
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.name = "pata_platform",
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.id = 0,
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.num_resources = ARRAY_SIZE(cf_resources),
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.resource = cf_resources,
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};
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static struct platform_device *sh2007_devices[] __initdata = {
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&smsc9118_0_device,
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&smsc9118_1_device,
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&cf_device,
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};
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static int __init sh2007_io_init(void)
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{
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platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices));
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return 0;
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}
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subsys_initcall(sh2007_io_init);
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static void __init sh2007_init_irq(void)
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{
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plat_irq_setup_pins(IRQ_MODE_IRQ);
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}
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/*
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* Initialize the board
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*/
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static void __init sh2007_setup(char **cmdline_p)
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{
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printk(KERN_INFO "SH-2007 Setup...");
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/* setup wait control registers for area 5 */
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__raw_writel(CS5BCR_D, CS5BCR);
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__raw_writel(CS5WCR_D, CS5WCR);
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__raw_writel(CS5PCR_D, CS5PCR);
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printk(KERN_INFO " done.\n");
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}
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/*
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* The Machine Vector
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*/
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struct sh_machine_vector mv_sh2007 __initmv = {
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.mv_setup = sh2007_setup,
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.mv_name = "sh2007",
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.mv_init_irq = sh2007_init_irq,
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,117 @@
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#ifndef __MACH_SH2007_H
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#define __MACH_SH2007_H
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#define CS5BCR 0xff802050
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#define CS5WCR 0xff802058
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#define CS5PCR 0xff802070
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#define BUS_SZ8 1
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#define BUS_SZ16 2
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#define BUS_SZ32 3
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#define PCMCIA_IODYN 1
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#define PCMCIA_ATA 0
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#define PCMCIA_IO8 2
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#define PCMCIA_IO16 3
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#define PCMCIA_COMM8 4
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#define PCMCIA_COMM16 5
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#define PCMCIA_ATTR8 6
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#define PCMCIA_ATTR16 7
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#define TYPE_SRAM 0
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#define TYPE_PCMCIA 4
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/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWW5 0
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#define IWW6 3
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/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRWD5 2
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#define IWRWD6 2
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/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRWS5 2
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#define IWRWS6 2
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/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRRD5 2
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#define IWRRD6 2
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/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
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#define IWRRS5 0
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#define IWRRS6 2
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/* burst count (0-3:4,8,16,32) */
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#define BST5 0
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#define BST6 0
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/* bus size */
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#define SZ5 BUS_SZ16
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#define SZ6 BUS_SZ16
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/* RD hold for SRAM (0-1:0,1) */
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#define RDSPL5 0
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#define RDSPL6 0
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/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
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#define BW5 0
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#define BW6 0
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/* Multiplex (0-1:0,1) */
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#define MPX5 0
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#define MPX6 0
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/* device type */
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#define TYPE5 TYPE_PCMCIA
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#define TYPE6 TYPE_PCMCIA
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/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define ADS5 0
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#define ADS6 0
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/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define ADH5 0
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#define ADH6 0
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/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define RDS5 0
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#define RDS6 0
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/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define RDH5 0
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#define RDH6 0
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/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define WTS5 0
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#define WTS6 0
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/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
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#define WTH5 0
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#define WTH6 0
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/* BS hold (0-1:1,2) */
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#define BSH5 0
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#define BSH6 0
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/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
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#define IW5 6 /* 60ns PIO mode 4 */
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#define IW6 15 /* 250ns */
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#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */
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#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */
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#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */
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#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */
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/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
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#define PCIW5 12
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/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
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#define TEDA5 2
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/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
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#define TEDB5 4
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/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
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#define TEHA5 2
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/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
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#define TEHB5 3
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#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \
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(IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \
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(SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
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#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \
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(RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
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#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \
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(PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \
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(TEDB5<<8)|(TEHA5<<4)|TEHB5)
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#define SMC0_BASE 0xb0800000 /* eth0 */
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#define SMC1_BASE 0xb0900000 /* eth1 */
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#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */
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#define IDE_BASE 0xb4000000 /* IDE */
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#define PC104_IO_BASE 0xb8000000
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#define PC104_MEM_BASE 0xba000000
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#define SMC_IO_SIZE 0x100
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#define CF_OFFSET 0x1f0
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#define IDE_OFFSET 0x170
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#endif /* __MACH_SH2007_H */
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@ -52,6 +52,7 @@ MIGOR SH_MIGOR
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RSK7201 SH_RSK7201
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RSK7203 SH_RSK7203
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AP325RXA SH_AP325RXA
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SH2007 SH_SH2007
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SH7763RDP SH_SH7763RDP
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SH7785LCR SH_SH7785LCR
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SH7785LCR_PT SH_SH7785LCR_PT
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@ -140,7 +140,15 @@
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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#if defined(CONFIG_SH_SH2007)
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
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# define SCSCR_INIT(port) 0x38
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#else
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/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
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# define SCSCR_INIT(port) 0x3a
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
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@ -599,9 +607,10 @@ static inline int sci_rxd_in(struct uart_port *port)
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* -- Mitch Davis - 15 Jul 2000
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*/
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#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)) && \
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!defined(CONFIG_SH_SH2007)
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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