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powerpc/mm/radix: Synchronize updates to the process table
When writing to the process table, we need to ensure the store is visible to a subsequent access by the MMU. We assume we never have the PID active while doing the update, so a ptesync/isync pair should hopefully be a big enough hammer for our purpose. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -138,6 +138,14 @@ static int radix__init_new_context(struct mm_struct *mm)
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rts_field = radix__get_tree_size();
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process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE);
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/*
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* Order the above store with subsequent update of the PID
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* register (at which point HW can start loading/caching
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* the entry) and the corresponding load by the MMU from
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* the L2 cache.
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*/
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asm volatile("ptesync;isync" : : : "memory");
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mm->context.npu_context = NULL;
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return index;
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