mirror of https://gitee.com/openkylin/linux.git
fm10k: Add Tx/Rx hardware ring bring-up/tear-down
This patch adds support for allocating, configuring, and freeing Tx/Rx ring resources. With these changes in place the descriptor queues are in a state where they are ready to transmit or receive if provided buffers. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck
Jeff Kirsher
parent
b7d8514c23
commit
3abaae42e1
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@ -407,6 +407,14 @@ void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
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/* Netdev */
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struct net_device *fm10k_alloc_netdev(void);
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int fm10k_setup_rx_resources(struct fm10k_ring *);
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int fm10k_setup_tx_resources(struct fm10k_ring *);
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void fm10k_free_rx_resources(struct fm10k_ring *);
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void fm10k_free_tx_resources(struct fm10k_ring *);
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void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
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void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
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void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
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struct fm10k_tx_buffer *);
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void fm10k_restore_rx_state(struct fm10k_intfc *);
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void fm10k_reset_rx_state(struct fm10k_intfc *);
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int fm10k_open(struct net_device *netdev);
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@ -19,6 +19,332 @@
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*/
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#include "fm10k.h"
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#include <linux/vmalloc.h>
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/**
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* fm10k_setup_tx_resources - allocate Tx resources (Descriptors)
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* @tx_ring: tx descriptor ring (for a specific queue) to setup
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*
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* Return 0 on success, negative on failure
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**/
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int fm10k_setup_tx_resources(struct fm10k_ring *tx_ring)
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{
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struct device *dev = tx_ring->dev;
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int size;
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size = sizeof(struct fm10k_tx_buffer) * tx_ring->count;
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tx_ring->tx_buffer = vzalloc(size);
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if (!tx_ring->tx_buffer)
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goto err;
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u64_stats_init(&tx_ring->syncp);
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/* round up to nearest 4K */
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tx_ring->size = tx_ring->count * sizeof(struct fm10k_tx_desc);
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tx_ring->size = ALIGN(tx_ring->size, 4096);
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tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
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&tx_ring->dma, GFP_KERNEL);
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if (!tx_ring->desc)
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goto err;
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return 0;
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err:
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vfree(tx_ring->tx_buffer);
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tx_ring->tx_buffer = NULL;
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return -ENOMEM;
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}
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/**
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* fm10k_setup_all_tx_resources - allocate all queues Tx resources
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* @interface: board private structure
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*
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* If this function returns with an error, then it's possible one or
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* more of the rings is populated (while the rest are not). It is the
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* callers duty to clean those orphaned rings.
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*
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* Return 0 on success, negative on failure
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**/
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static int fm10k_setup_all_tx_resources(struct fm10k_intfc *interface)
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{
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int i, err = 0;
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for (i = 0; i < interface->num_tx_queues; i++) {
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err = fm10k_setup_tx_resources(interface->tx_ring[i]);
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if (!err)
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continue;
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netif_err(interface, probe, interface->netdev,
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"Allocation for Tx Queue %u failed\n", i);
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goto err_setup_tx;
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}
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return 0;
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err_setup_tx:
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/* rewind the index freeing the rings as we go */
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while (i--)
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fm10k_free_tx_resources(interface->tx_ring[i]);
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return err;
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}
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/**
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* fm10k_setup_rx_resources - allocate Rx resources (Descriptors)
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* @rx_ring: rx descriptor ring (for a specific queue) to setup
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*
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* Returns 0 on success, negative on failure
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**/
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int fm10k_setup_rx_resources(struct fm10k_ring *rx_ring)
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{
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struct device *dev = rx_ring->dev;
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int size;
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size = sizeof(struct fm10k_rx_buffer) * rx_ring->count;
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rx_ring->rx_buffer = vzalloc(size);
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if (!rx_ring->rx_buffer)
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goto err;
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u64_stats_init(&rx_ring->syncp);
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/* Round up to nearest 4K */
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rx_ring->size = rx_ring->count * sizeof(union fm10k_rx_desc);
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rx_ring->size = ALIGN(rx_ring->size, 4096);
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rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
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&rx_ring->dma, GFP_KERNEL);
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if (!rx_ring->desc)
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goto err;
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return 0;
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err:
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vfree(rx_ring->rx_buffer);
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rx_ring->rx_buffer = NULL;
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return -ENOMEM;
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}
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/**
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* fm10k_setup_all_rx_resources - allocate all queues Rx resources
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* @interface: board private structure
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*
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* If this function returns with an error, then it's possible one or
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* more of the rings is populated (while the rest are not). It is the
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* callers duty to clean those orphaned rings.
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*
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* Return 0 on success, negative on failure
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**/
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static int fm10k_setup_all_rx_resources(struct fm10k_intfc *interface)
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{
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int i, err = 0;
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for (i = 0; i < interface->num_rx_queues; i++) {
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err = fm10k_setup_rx_resources(interface->rx_ring[i]);
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if (!err)
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continue;
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netif_err(interface, probe, interface->netdev,
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"Allocation for Rx Queue %u failed\n", i);
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goto err_setup_rx;
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}
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return 0;
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err_setup_rx:
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/* rewind the index freeing the rings as we go */
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while (i--)
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fm10k_free_rx_resources(interface->rx_ring[i]);
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return err;
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}
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void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *ring,
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struct fm10k_tx_buffer *tx_buffer)
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{
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if (tx_buffer->skb) {
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dev_kfree_skb_any(tx_buffer->skb);
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if (dma_unmap_len(tx_buffer, len))
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dma_unmap_single(ring->dev,
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dma_unmap_addr(tx_buffer, dma),
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dma_unmap_len(tx_buffer, len),
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DMA_TO_DEVICE);
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} else if (dma_unmap_len(tx_buffer, len)) {
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dma_unmap_page(ring->dev,
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dma_unmap_addr(tx_buffer, dma),
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dma_unmap_len(tx_buffer, len),
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DMA_TO_DEVICE);
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}
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tx_buffer->next_to_watch = NULL;
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tx_buffer->skb = NULL;
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dma_unmap_len_set(tx_buffer, len, 0);
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/* tx_buffer must be completely set up in the transmit path */
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}
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/**
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* fm10k_clean_tx_ring - Free Tx Buffers
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* @tx_ring: ring to be cleaned
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**/
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static void fm10k_clean_tx_ring(struct fm10k_ring *tx_ring)
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{
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struct fm10k_tx_buffer *tx_buffer;
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unsigned long size;
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u16 i;
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/* ring already cleared, nothing to do */
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if (!tx_ring->tx_buffer)
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return;
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/* Free all the Tx ring sk_buffs */
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for (i = 0; i < tx_ring->count; i++) {
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tx_buffer = &tx_ring->tx_buffer[i];
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fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer);
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}
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/* reset BQL values */
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netdev_tx_reset_queue(txring_txq(tx_ring));
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size = sizeof(struct fm10k_tx_buffer) * tx_ring->count;
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memset(tx_ring->tx_buffer, 0, size);
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/* Zero out the descriptor ring */
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memset(tx_ring->desc, 0, tx_ring->size);
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}
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/**
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* fm10k_free_tx_resources - Free Tx Resources per Queue
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* @tx_ring: Tx descriptor ring for a specific queue
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*
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* Free all transmit software resources
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**/
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void fm10k_free_tx_resources(struct fm10k_ring *tx_ring)
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{
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fm10k_clean_tx_ring(tx_ring);
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vfree(tx_ring->tx_buffer);
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tx_ring->tx_buffer = NULL;
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/* if not set, then don't free */
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if (!tx_ring->desc)
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return;
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dma_free_coherent(tx_ring->dev, tx_ring->size,
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tx_ring->desc, tx_ring->dma);
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tx_ring->desc = NULL;
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}
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/**
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* fm10k_clean_all_tx_rings - Free Tx Buffers for all queues
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* @interface: board private structure
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**/
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void fm10k_clean_all_tx_rings(struct fm10k_intfc *interface)
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{
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int i;
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for (i = 0; i < interface->num_tx_queues; i++)
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fm10k_clean_tx_ring(interface->tx_ring[i]);
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}
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/**
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* fm10k_free_all_tx_resources - Free Tx Resources for All Queues
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* @interface: board private structure
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*
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* Free all transmit software resources
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**/
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static void fm10k_free_all_tx_resources(struct fm10k_intfc *interface)
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{
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int i = interface->num_tx_queues;
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while (i--)
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fm10k_free_tx_resources(interface->tx_ring[i]);
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}
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/**
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* fm10k_clean_rx_ring - Free Rx Buffers per Queue
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* @rx_ring: ring to free buffers from
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**/
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static void fm10k_clean_rx_ring(struct fm10k_ring *rx_ring)
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{
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unsigned long size;
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u16 i;
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if (!rx_ring->rx_buffer)
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return;
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if (rx_ring->skb)
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dev_kfree_skb(rx_ring->skb);
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rx_ring->skb = NULL;
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/* Free all the Rx ring sk_buffs */
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for (i = 0; i < rx_ring->count; i++) {
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struct fm10k_rx_buffer *buffer = &rx_ring->rx_buffer[i];
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/* clean-up will only set page pointer to NULL */
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if (!buffer->page)
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continue;
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dma_unmap_page(rx_ring->dev, buffer->dma,
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PAGE_SIZE, DMA_FROM_DEVICE);
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__free_page(buffer->page);
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buffer->page = NULL;
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}
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size = sizeof(struct fm10k_rx_buffer) * rx_ring->count;
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memset(rx_ring->rx_buffer, 0, size);
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/* Zero out the descriptor ring */
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memset(rx_ring->desc, 0, rx_ring->size);
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rx_ring->next_to_alloc = 0;
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rx_ring->next_to_clean = 0;
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rx_ring->next_to_use = 0;
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}
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/**
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* fm10k_free_rx_resources - Free Rx Resources
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* @rx_ring: ring to clean the resources from
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*
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* Free all receive software resources
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**/
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void fm10k_free_rx_resources(struct fm10k_ring *rx_ring)
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{
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fm10k_clean_rx_ring(rx_ring);
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vfree(rx_ring->rx_buffer);
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rx_ring->rx_buffer = NULL;
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/* if not set, then don't free */
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if (!rx_ring->desc)
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return;
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dma_free_coherent(rx_ring->dev, rx_ring->size,
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rx_ring->desc, rx_ring->dma);
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rx_ring->desc = NULL;
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}
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/**
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* fm10k_clean_all_rx_rings - Free Rx Buffers for all queues
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* @interface: board private structure
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**/
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void fm10k_clean_all_rx_rings(struct fm10k_intfc *interface)
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{
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int i;
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for (i = 0; i < interface->num_rx_queues; i++)
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fm10k_clean_rx_ring(interface->rx_ring[i]);
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}
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/**
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* fm10k_free_all_rx_resources - Free Rx Resources for All Queues
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* @interface: board private structure
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*
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* Free all receive software resources
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**/
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static void fm10k_free_all_rx_resources(struct fm10k_intfc *interface)
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{
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int i = interface->num_rx_queues;
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while (i--)
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fm10k_free_rx_resources(interface->rx_ring[i]);
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}
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/**
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* fm10k_request_glort_range - Request GLORTs for use in configuring rules
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@ -59,6 +385,16 @@ int fm10k_open(struct net_device *netdev)
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struct fm10k_intfc *interface = netdev_priv(netdev);
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int err;
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/* allocate transmit descriptors */
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err = fm10k_setup_all_tx_resources(interface);
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if (err)
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goto err_setup_tx;
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/* allocate receive descriptors */
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err = fm10k_setup_all_rx_resources(interface);
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if (err)
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goto err_setup_rx;
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/* allocate interrupt resources */
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err = fm10k_qv_request_irq(interface);
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if (err)
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@ -81,6 +417,10 @@ int fm10k_open(struct net_device *netdev)
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err_set_queues:
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fm10k_qv_free_irq(interface);
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err_req_irq:
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fm10k_free_all_rx_resources(interface);
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err_setup_rx:
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fm10k_free_all_tx_resources(interface);
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err_setup_tx:
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return err;
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}
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@ -103,6 +443,9 @@ int fm10k_close(struct net_device *netdev)
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fm10k_qv_free_irq(interface);
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fm10k_free_all_tx_resources(interface);
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fm10k_free_all_rx_resources(interface);
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return 0;
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}
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@ -485,6 +485,299 @@ static void fm10k_service_task(struct work_struct *work)
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fm10k_service_event_complete(interface);
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}
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/**
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* fm10k_configure_tx_ring - Configure Tx ring after Reset
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* @interface: board private structure
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* @ring: structure containing ring specific data
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*
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* Configure the Tx descriptor ring after a reset.
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**/
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static void fm10k_configure_tx_ring(struct fm10k_intfc *interface,
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struct fm10k_ring *ring)
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{
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struct fm10k_hw *hw = &interface->hw;
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u64 tdba = ring->dma;
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u32 size = ring->count * sizeof(struct fm10k_tx_desc);
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u32 txint = FM10K_INT_MAP_DISABLE;
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u32 txdctl = FM10K_TXDCTL_ENABLE | (1 << FM10K_TXDCTL_MAX_TIME_SHIFT);
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u8 reg_idx = ring->reg_idx;
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/* disable queue to avoid issues while updating state */
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fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
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fm10k_write_flush(hw);
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/* possible poll here to verify ring resources have been cleaned */
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/* set location and size for descriptor ring */
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fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
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fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
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fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
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/* reset head and tail pointers */
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fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
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fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
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/* store tail pointer */
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ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)];
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/* reset ntu and ntc to place SW in sync with hardwdare */
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ring->next_to_clean = 0;
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ring->next_to_use = 0;
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/* Map interrupt */
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if (ring->q_vector) {
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txint = ring->q_vector->v_idx + NON_Q_VECTORS(hw);
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txint |= FM10K_INT_MAP_TIMER0;
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}
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fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);
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/* enable use of FTAG bit in Tx descriptor, register is RO for VF */
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fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),
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FM10K_PFVTCTL_FTAG_DESC_ENABLE);
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/* enable queue */
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fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);
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}
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/**
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* fm10k_enable_tx_ring - Verify Tx ring is enabled after configuration
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* @interface: board private structure
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* @ring: structure containing ring specific data
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*
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* Verify the Tx descriptor ring is ready for transmit.
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**/
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static void fm10k_enable_tx_ring(struct fm10k_intfc *interface,
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struct fm10k_ring *ring)
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{
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struct fm10k_hw *hw = &interface->hw;
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int wait_loop = 10;
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u32 txdctl;
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u8 reg_idx = ring->reg_idx;
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/* if we are already enabled just exit */
|
||||
if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE)
|
||||
return;
|
||||
|
||||
/* poll to verify queue is enabled */
|
||||
do {
|
||||
usleep_range(1000, 2000);
|
||||
txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx));
|
||||
} while (!(txdctl & FM10K_TXDCTL_ENABLE) && --wait_loop);
|
||||
if (!wait_loop)
|
||||
netif_err(interface, drv, interface->netdev,
|
||||
"Could not enable Tx Queue %d\n", reg_idx);
|
||||
}
|
||||
|
||||
/**
|
||||
* fm10k_configure_tx - Configure Transmit Unit after Reset
|
||||
* @interface: board private structure
|
||||
*
|
||||
* Configure the Tx unit of the MAC after a reset.
|
||||
**/
|
||||
static void fm10k_configure_tx(struct fm10k_intfc *interface)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Setup the HW Tx Head and Tail descriptor pointers */
|
||||
for (i = 0; i < interface->num_tx_queues; i++)
|
||||
fm10k_configure_tx_ring(interface, interface->tx_ring[i]);
|
||||
|
||||
/* poll here to verify that Tx rings are now enabled */
|
||||
for (i = 0; i < interface->num_tx_queues; i++)
|
||||
fm10k_enable_tx_ring(interface, interface->tx_ring[i]);
|
||||
}
|
||||
|
||||
/**
|
||||
* fm10k_configure_rx_ring - Configure Rx ring after Reset
|
||||
* @interface: board private structure
|
||||
* @ring: structure containing ring specific data
|
||||
*
|
||||
* Configure the Rx descriptor ring after a reset.
|
||||
**/
|
||||
static void fm10k_configure_rx_ring(struct fm10k_intfc *interface,
|
||||
struct fm10k_ring *ring)
|
||||
{
|
||||
u64 rdba = ring->dma;
|
||||
struct fm10k_hw *hw = &interface->hw;
|
||||
u32 size = ring->count * sizeof(union fm10k_rx_desc);
|
||||
u32 rxqctl = FM10K_RXQCTL_ENABLE | FM10K_RXQCTL_PF;
|
||||
u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
|
||||
u32 srrctl = FM10K_SRRCTL_BUFFER_CHAINING_EN;
|
||||
u32 rxint = FM10K_INT_MAP_DISABLE;
|
||||
u8 rx_pause = interface->rx_pause;
|
||||
u8 reg_idx = ring->reg_idx;
|
||||
|
||||
/* disable queue to avoid issues while updating state */
|
||||
fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), 0);
|
||||
fm10k_write_flush(hw);
|
||||
|
||||
/* possible poll here to verify ring resources have been cleaned */
|
||||
|
||||
/* set location and size for descriptor ring */
|
||||
fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
|
||||
fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);
|
||||
fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);
|
||||
|
||||
/* reset head and tail pointers */
|
||||
fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);
|
||||
fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);
|
||||
|
||||
/* store tail pointer */
|
||||
ring->tail = &interface->uc_addr[FM10K_RDT(reg_idx)];
|
||||
|
||||
/* reset ntu and ntc to place SW in sync with hardwdare */
|
||||
ring->next_to_clean = 0;
|
||||
ring->next_to_use = 0;
|
||||
ring->next_to_alloc = 0;
|
||||
|
||||
/* Configure the Rx buffer size for one buff without split */
|
||||
srrctl |= FM10K_RX_BUFSZ >> FM10K_SRRCTL_BSIZEPKT_SHIFT;
|
||||
|
||||
/* Configure the Rx ring to supress loopback packets */
|
||||
srrctl |= FM10K_SRRCTL_LOOPBACK_SUPPRESS;
|
||||
fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);
|
||||
|
||||
/* Enable drop on empty */
|
||||
#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
|
||||
if (interface->pfc_en)
|
||||
rx_pause = interface->pfc_en;
|
||||
#endif
|
||||
if (!(rx_pause & (1 << ring->qos_pc)))
|
||||
rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
|
||||
|
||||
fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
|
||||
|
||||
/* assign default VLAN to queue */
|
||||
ring->vid = hw->mac.default_vid;
|
||||
|
||||
/* Map interrupt */
|
||||
if (ring->q_vector) {
|
||||
rxint = ring->q_vector->v_idx + NON_Q_VECTORS(hw);
|
||||
rxint |= FM10K_INT_MAP_TIMER1;
|
||||
}
|
||||
|
||||
fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);
|
||||
|
||||
/* enable queue */
|
||||
fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
|
||||
}
|
||||
|
||||
/**
|
||||
* fm10k_update_rx_drop_en - Configures the drop enable bits for Rx rings
|
||||
* @interface: board private structure
|
||||
*
|
||||
* Configure the drop enable bits for the Rx rings.
|
||||
**/
|
||||
void fm10k_update_rx_drop_en(struct fm10k_intfc *interface)
|
||||
{
|
||||
struct fm10k_hw *hw = &interface->hw;
|
||||
u8 rx_pause = interface->rx_pause;
|
||||
int i;
|
||||
|
||||
#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
|
||||
if (interface->pfc_en)
|
||||
rx_pause = interface->pfc_en;
|
||||
|
||||
#endif
|
||||
for (i = 0; i < interface->num_rx_queues; i++) {
|
||||
struct fm10k_ring *ring = interface->rx_ring[i];
|
||||
u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
|
||||
u8 reg_idx = ring->reg_idx;
|
||||
|
||||
if (!(rx_pause & (1 << ring->qos_pc)))
|
||||
rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
|
||||
|
||||
fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* fm10k_configure_dglort - Configure Receive DGLORT after reset
|
||||
* @interface: board private structure
|
||||
*
|
||||
* Configure the DGLORT description and RSS tables.
|
||||
**/
|
||||
static void fm10k_configure_dglort(struct fm10k_intfc *interface)
|
||||
{
|
||||
struct fm10k_dglort_cfg dglort = { 0 };
|
||||
struct fm10k_hw *hw = &interface->hw;
|
||||
int i;
|
||||
u32 mrqc;
|
||||
|
||||
/* Fill out hash function seeds */
|
||||
for (i = 0; i < FM10K_RSSRK_SIZE; i++)
|
||||
fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]);
|
||||
|
||||
/* Write RETA table to hardware */
|
||||
for (i = 0; i < FM10K_RETA_SIZE; i++)
|
||||
fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]);
|
||||
|
||||
/* Generate RSS hash based on packet types, TCP/UDP
|
||||
* port numbers and/or IPv4/v6 src and dst addresses
|
||||
*/
|
||||
mrqc = FM10K_MRQC_IPV4 |
|
||||
FM10K_MRQC_TCP_IPV4 |
|
||||
FM10K_MRQC_IPV6 |
|
||||
FM10K_MRQC_TCP_IPV6;
|
||||
|
||||
if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV4_UDP)
|
||||
mrqc |= FM10K_MRQC_UDP_IPV4;
|
||||
if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV6_UDP)
|
||||
mrqc |= FM10K_MRQC_UDP_IPV6;
|
||||
|
||||
fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);
|
||||
|
||||
/* configure default DGLORT mapping for RSS/DCB */
|
||||
dglort.inner_rss = 1;
|
||||
dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
|
||||
dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
|
||||
hw->mac.ops.configure_dglort_map(hw, &dglort);
|
||||
|
||||
/* assign GLORT per queue for queue mapped testing */
|
||||
if (interface->glort_count > 64) {
|
||||
memset(&dglort, 0, sizeof(dglort));
|
||||
dglort.inner_rss = 1;
|
||||
dglort.glort = interface->glort + 64;
|
||||
dglort.idx = fm10k_dglort_pf_queue;
|
||||
dglort.queue_l = fls(interface->num_rx_queues - 1);
|
||||
hw->mac.ops.configure_dglort_map(hw, &dglort);
|
||||
}
|
||||
|
||||
/* assign glort value for RSS/DCB specific to this interface */
|
||||
memset(&dglort, 0, sizeof(dglort));
|
||||
dglort.inner_rss = 1;
|
||||
dglort.glort = interface->glort;
|
||||
dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
|
||||
dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
|
||||
/* configure DGLORT mapping for RSS/DCB */
|
||||
dglort.idx = fm10k_dglort_pf_rss;
|
||||
hw->mac.ops.configure_dglort_map(hw, &dglort);
|
||||
}
|
||||
|
||||
/**
|
||||
* fm10k_configure_rx - Configure Receive Unit after Reset
|
||||
* @interface: board private structure
|
||||
*
|
||||
* Configure the Rx unit of the MAC after a reset.
|
||||
**/
|
||||
static void fm10k_configure_rx(struct fm10k_intfc *interface)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure SWPRI to PC map */
|
||||
fm10k_configure_swpri_map(interface);
|
||||
|
||||
/* Configure RSS and DGLORT map */
|
||||
fm10k_configure_dglort(interface);
|
||||
|
||||
/* Setup the HW Rx Head and Tail descriptor pointers */
|
||||
for (i = 0; i < interface->num_rx_queues; i++)
|
||||
fm10k_configure_rx_ring(interface, interface->rx_ring[i]);
|
||||
|
||||
/* possible poll here to verify that Rx rings are now enabled */
|
||||
}
|
||||
|
||||
static void fm10k_napi_enable_all(struct fm10k_intfc *interface)
|
||||
{
|
||||
struct fm10k_q_vector *q_vector;
|
||||
|
|
@ -970,6 +1263,12 @@ void fm10k_up(struct fm10k_intfc *interface)
|
|||
/* Enable Tx/Rx DMA */
|
||||
hw->mac.ops.start_hw(hw);
|
||||
|
||||
/* configure Tx descriptor rings */
|
||||
fm10k_configure_tx(interface);
|
||||
|
||||
/* configure Rx descriptor rings */
|
||||
fm10k_configure_rx(interface);
|
||||
|
||||
/* configure interrupts */
|
||||
hw->mac.ops.update_int_moderator(hw);
|
||||
|
||||
|
|
@ -1031,6 +1330,9 @@ void fm10k_down(struct fm10k_intfc *interface)
|
|||
|
||||
/* Disable DMA engine for Tx/Rx */
|
||||
hw->mac.ops.stop_hw(hw);
|
||||
|
||||
/* free any buffers still on the rings */
|
||||
fm10k_clean_all_tx_rings(interface);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue