mirror of https://gitee.com/openkylin/linux.git
DMAENGINE: ste_dma40: removed a few magic numbers
Make sure to extract the revision field explicitly and document what bits are being accessed here without magic numbers. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -41,7 +41,7 @@
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#define D40_ALLOC_LOG_FREE 0
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/* Hardware designer of the block */
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#define D40_PERIPHID2_DESIGNER 0x8
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#define D40_HW_DESIGNER 0x8
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/**
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* enum 40_command - The different commands and/or statuses.
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@ -2438,6 +2438,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
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int num_phy_chans;
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int i;
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u32 val;
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u32 rev;
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clk = clk_get(&pdev->dev, NULL);
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@ -2476,21 +2477,26 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
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}
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}
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/* Get silicon revision */
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/* Get silicon revision and designer */
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val = readl(virtbase + D40_DREG_PERIPHID2);
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if ((val & 0xf) != D40_PERIPHID2_DESIGNER) {
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if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
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D40_HW_DESIGNER) {
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dev_err(&pdev->dev,
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"[%s] Unknown designer! Got %x wanted %x\n",
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__func__, val & 0xf, D40_PERIPHID2_DESIGNER);
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__func__, val & D40_DREG_PERIPHID2_DESIGNER_MASK,
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D40_HW_DESIGNER);
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goto failure;
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}
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rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
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D40_DREG_PERIPHID2_REV_POS;
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/* The number of physical channels on this HW */
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num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
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dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
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(val >> 4) & 0xf, res->start);
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rev, res->start);
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plat_data = pdev->dev.platform_data;
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@ -2512,7 +2518,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
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goto failure;
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}
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base->rev = (val >> 4) & 0xf;
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base->rev = rev;
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base->clk = clk;
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base->num_phy_chans = num_phy_chans;
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base->num_log_chans = num_log_chans;
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@ -163,6 +163,9 @@
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#define D40_DREG_PERIPHID0 0xFE0
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#define D40_DREG_PERIPHID1 0xFE4
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#define D40_DREG_PERIPHID2 0xFE8
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#define D40_DREG_PERIPHID2_REV_POS 4
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#define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS)
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#define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf
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#define D40_DREG_PERIPHID3 0xFEC
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#define D40_DREG_CELLID0 0xFF0
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#define D40_DREG_CELLID1 0xFF4
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