mirror of https://gitee.com/openkylin/linux.git
e1000e: cleanup ethtool loopback setup code
Refactor the loopback setup code to first handle the only 10/100 PHY supported by the driver if applicable and then handle the 1Gig PHYs in a switch statement for PHY-specific setups. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Emil Tantilov <emil.s.tantilov@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1263,33 +1263,36 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
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hw->mac.autoneg = 0;
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/* Workaround: K1 must be disabled for stable 1Gbps operation */
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if (hw->mac.type == e1000_pchlan)
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e1000_configure_k1_ich8lan(hw, false);
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if (hw->phy.type == e1000_phy_ife) {
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/* force 100, set loopback */
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e1e_wphy(hw, PHY_CONTROL, 0x6100);
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if (hw->phy.type == e1000_phy_m88) {
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/* Now set up the MAC to the same speed/duplex as the PHY. */
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ctrl_reg = er32(CTRL);
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ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
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ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
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E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
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E1000_CTRL_SPD_100 |/* Force Speed to 100 */
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E1000_CTRL_FD); /* Force Duplex to FULL */
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ew32(CTRL, ctrl_reg);
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udelay(500);
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return 0;
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}
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/* Specific PHY configuration for loopback */
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switch (hw->phy.type) {
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case e1000_phy_m88:
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/* Auto-MDI/MDIX Off */
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e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
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/* reset to update Auto-MDI/MDIX */
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e1e_wphy(hw, PHY_CONTROL, 0x9140);
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/* autoneg off */
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e1e_wphy(hw, PHY_CONTROL, 0x8140);
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} else if (hw->phy.type == e1000_phy_gg82563)
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break;
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case e1000_phy_gg82563:
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e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 0x1CC);
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ctrl_reg = er32(CTRL);
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switch (hw->phy.type) {
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case e1000_phy_ife:
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/* force 100, set loopback */
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e1e_wphy(hw, PHY_CONTROL, 0x6100);
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/* Now set up the MAC to the same speed/duplex as the PHY. */
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ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
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ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
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E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
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E1000_CTRL_SPD_100 |/* Force Speed to 100 */
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E1000_CTRL_FD); /* Force Duplex to FULL */
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break;
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case e1000_phy_bm:
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/* Set Default MAC Interface speed to 1GB */
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@ -1312,24 +1315,31 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
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/* Set Early Link Enable */
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e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
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e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400);
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/* fall through */
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break;
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case e1000_phy_82577:
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case e1000_phy_82578:
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/* Workaround: K1 must be disabled for stable 1Gbps operation */
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e1000_configure_k1_ich8lan(hw, false);
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break;
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default:
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/* force 1000, set loopback */
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e1e_wphy(hw, PHY_CONTROL, 0x4140);
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mdelay(250);
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/* Now set up the MAC to the same speed/duplex as the PHY. */
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ctrl_reg = er32(CTRL);
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ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
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ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
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E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
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E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
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E1000_CTRL_FD); /* Force Duplex to FULL */
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if (adapter->flags & FLAG_IS_ICH)
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ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */
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break;
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}
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/* force 1000, set loopback */
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e1e_wphy(hw, PHY_CONTROL, 0x4140);
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mdelay(250);
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/* Now set up the MAC to the same speed/duplex as the PHY. */
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ctrl_reg = er32(CTRL);
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ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
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ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
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E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
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E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
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E1000_CTRL_FD); /* Force Duplex to FULL */
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if (adapter->flags & FLAG_IS_ICH)
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ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */
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if (hw->phy.media_type == e1000_media_type_copper &&
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hw->phy.type == e1000_phy_m88) {
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ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
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