mirror of https://gitee.com/openkylin/linux.git
drm/i915: move cpu_transcoder to the pipe configuration
For a bunch of reason we need to more accurately track this: - hw pipe state readout for Haswell needs the cpu transcoder. - We need to know the right cpu transcoder in a bunch of places in ->disable and other modeset callbacks. In the future we need to add hw state readout&check support, too. But to avoid ugly merge conflicts do the rote sed job now without any functional changes. v2: Preserve the cpu_transcoder value when overwriting crtc->config. Reported by Paulo. Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) [danvet: Removed rough whitespace that Chris spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
dc4bd2d109
commit
3b117c8f28
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@ -924,7 +924,7 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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int type = intel_encoder->type;
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uint32_t temp;
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@ -958,7 +958,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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uint32_t temp;
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@ -1223,7 +1223,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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if (cpu_transcoder != TRANSCODER_EDP)
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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@ -1233,7 +1233,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
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void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
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{
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struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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if (cpu_transcoder != TRANSCODER_EDP)
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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@ -892,7 +892,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
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struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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return intel_crtc->cpu_transcoder;
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return intel_crtc->config.cpu_transcoder;
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}
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static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
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@ -3203,7 +3203,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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assert_transcoder_disabled(dev_priv, TRANSCODER_A);
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@ -3578,7 +3578,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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struct intel_encoder *encoder;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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if (!intel_crtc->active)
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return;
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@ -3638,7 +3638,7 @@ static void haswell_crtc_off(struct drm_crtc *crtc)
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/* Stop saying we're using TRANSCODER_EDP because some other CRTC might
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* start using it. */
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intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
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intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
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intel_ddi_put_crtc_pll(crtc);
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}
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@ -4494,7 +4494,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum pipe pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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uint32_t vsyncshift;
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if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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@ -5236,7 +5236,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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uint32_t val;
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val = I915_READ(PIPECONF(cpu_transcoder));
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@ -5430,7 +5430,7 @@ void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe = crtc->pipe;
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enum transcoder transcoder = crtc->cpu_transcoder;
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enum transcoder transcoder = crtc->config.cpu_transcoder;
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if (INTEL_INFO(dev)->gen >= 5) {
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I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
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@ -5613,7 +5613,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
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WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
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"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
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intel_crtc->cpu_transcoder = pipe;
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intel_crtc->config.cpu_transcoder = pipe;
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ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
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&has_reduced_clock, &reduced_clock);
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@ -5797,9 +5797,9 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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}
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if (is_cpu_edp)
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intel_crtc->cpu_transcoder = TRANSCODER_EDP;
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intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
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else
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intel_crtc->cpu_transcoder = pipe;
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intel_crtc->config.cpu_transcoder = pipe;
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/* We are not sure yet this won't happen. */
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WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
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@ -5808,7 +5808,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
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num_connectors, pipe_name(pipe));
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WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
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WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
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(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
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WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
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@ -5859,7 +5859,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
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tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder));
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if (!(tmp & PIPECONF_ENABLE))
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return false;
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@ -6827,7 +6827,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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struct drm_display_mode *mode;
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int htot = I915_READ(HTOTAL(cpu_transcoder));
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int hsync = I915_READ(HSYNC(cpu_transcoder));
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@ -7990,10 +7990,12 @@ static int __intel_set_mode(struct drm_crtc *crtc,
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* to set it here already despite that we pass it down the callchain.
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*/
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if (modeset_pipes) {
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enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
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crtc->mode = *mode;
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/* mode_set/enable/disable functions rely on a correct pipe
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* config. */
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to_intel_crtc(crtc)->config = *pipe_config;
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to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
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}
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/* Only after disabling all output pipelines that will be changed can we
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@ -8404,7 +8406,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
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/* Swap pipes & planes for FBC on pre-965 */
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intel_crtc->pipe = pipe;
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intel_crtc->plane = pipe;
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intel_crtc->cpu_transcoder = pipe;
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intel_crtc->config.cpu_transcoder = pipe;
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if (IS_MOBILE(dev) && IS_GEN3(dev)) {
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DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
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intel_crtc->plane = !pipe;
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@ -9129,7 +9131,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
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u32 reg;
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/* Clear any frame start delays used for debugging left by the BIOS */
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reg = PIPECONF(crtc->cpu_transcoder);
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reg = PIPECONF(crtc->config.cpu_transcoder);
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I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
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/* We need to sanitize the plane -> pipe mapping first because this will
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@ -9295,7 +9297,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
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}
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crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
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crtc->cpu_transcoder = TRANSCODER_EDP;
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crtc->config.cpu_transcoder = TRANSCODER_EDP;
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DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
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pipe_name(pipe));
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@ -9305,7 +9307,10 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
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setup_pipes:
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list_for_each_entry(crtc, &dev->mode_config.crtc_list,
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base.head) {
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enum transcoder tmp = crtc->config.cpu_transcoder;
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memset(&crtc->config, 0, sizeof(crtc->config));
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crtc->config.cpu_transcoder = tmp;
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crtc->active = dev_priv->display.get_pipe_config(crtc,
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&crtc->config);
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@ -188,6 +188,10 @@ struct intel_crtc_config {
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* between pch encoders and cpu encoders. */
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bool has_pch_encoder;
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/* CPU Transcoder for the pipe. Currently this can only differ from the
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* pipe on Haswell (where we have a special eDP transcoder). */
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enum transcoder cpu_transcoder;
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/*
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* Use reduced/limited/broadcast rbg range, compressing from the full
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* range fed into the crtcs.
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@ -226,7 +230,6 @@ struct intel_crtc {
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struct drm_crtc base;
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enum pipe pipe;
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enum plane plane;
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enum transcoder cpu_transcoder;
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u8 lut_r[256], lut_g[256], lut_b[256];
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/*
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* Whether the crtc and the connected output pipeline is active. Implies
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@ -294,8 +294,8 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
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u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->cpu_transcoder);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
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u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
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unsigned int i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(ctl_reg);
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@ -570,7 +570,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->cpu_transcoder);
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u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
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u32 val = I915_READ(reg);
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assert_hdmi_port_disabled(intel_hdmi);
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