mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: Fix no display on Fiji
Allocate memory for the second pipe allocate_mem_input() needs to be done prior to program pipe front end. It shows sensitive to Fiji. Failure to do so will cause error in allocate memory allocate_mem_input() on the second connected display. Signed-off-by: Jerry Zuo <Jerry.Zuo@amd.com> Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1370,16 +1370,6 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
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/* mst support - use total stream count */
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if (pipe_ctx->plane_res.mi != NULL) {
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pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
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pipe_ctx->plane_res.mi,
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stream->timing.h_total,
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stream->timing.v_total,
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stream->timing.pix_clk_khz,
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context->stream_count);
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}
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pipe_ctx->stream->sink->link->psr_enabled = false;
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return DC_OK;
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@ -2891,6 +2881,15 @@ static void dce110_apply_ctx_for_surface(
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if (pipe_ctx->stream != stream)
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continue;
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/* Need to allocate mem before program front end for Fiji */
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if (pipe_ctx->plane_res.mi != NULL)
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pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
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pipe_ctx->plane_res.mi,
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pipe_ctx->stream->timing.h_total,
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pipe_ctx->stream->timing.v_total,
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pipe_ctx->stream->timing.pix_clk_khz,
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context->stream_count);
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dce110_program_front_end_for_pipe(dc, pipe_ctx);
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program_surface_visibility(dc, pipe_ctx);
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