mirror of https://gitee.com/openkylin/linux.git
soc: fsl: dpio: Replace QMAN array mode with ring mode enqueue
This change of algorithm will enable faster bulk enqueue. This will greatly benefit XDP bulk enqueue. Signed-off-by: Youri Querry <youri.querry_1@nxp.com> Acked-by: Roy Pledge <roy.pledge@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com>
This commit is contained in:
Youri Querry
Li Yang
parent
b46fe745e4
commit
3b2abda7d2
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@ -8,6 +8,7 @@
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#include <asm/cacheflush.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <soc/fsl/dpaa2-global.h>
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#include "qbman-portal.h"
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@ -21,6 +22,7 @@
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/* CINH register offsets */
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#define QBMAN_CINH_SWP_EQCR_PI 0x800
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#define QBMAN_CINH_SWP_EQCR_CI 0x840
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#define QBMAN_CINH_SWP_EQAR 0x8c0
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#define QBMAN_CINH_SWP_CR_RT 0x900
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#define QBMAN_CINH_SWP_VDQCR_RT 0x940
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@ -44,6 +46,8 @@
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#define QBMAN_CENA_SWP_CR 0x600
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#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
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#define QBMAN_CENA_SWP_VDQCR 0x780
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#define QBMAN_CENA_SWP_EQCR_CI 0x840
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#define QBMAN_CENA_SWP_EQCR_CI_MEMBACK 0x1840
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/* CENA register offsets in memory-backed mode */
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#define QBMAN_CENA_SWP_DQRR_MEM(n) (0x800 + ((u32)(n) << 6))
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@ -71,6 +75,12 @@
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/* opaque token for static dequeues */
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#define QMAN_SDQCR_TOKEN 0xbb
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#define QBMAN_EQCR_DCA_IDXMASK 0x0f
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#define QBMAN_ENQUEUE_FLAG_DCA (1ULL << 31)
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#define EQ_DESC_SIZE_WITHOUT_FD 29
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#define EQ_DESC_SIZE_FD_START 32
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enum qbman_sdqcr_dct {
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qbman_sdqcr_dct_null = 0,
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qbman_sdqcr_dct_prio_ics,
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@ -215,6 +225,15 @@ static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
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#define QMAN_RT_MODE 0x00000100
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static inline u8 qm_cyc_diff(u8 ringsize, u8 first, u8 last)
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{
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/* 'first' is included, 'last' is excluded */
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if (first <= last)
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return last - first;
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else
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return (2 * ringsize) - (first - last);
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}
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/**
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* qbman_swp_init() - Create a functional object representing the given
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* QBMan portal descriptor.
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@ -227,6 +246,10 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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{
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struct qbman_swp *p = kzalloc(sizeof(*p), GFP_KERNEL);
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u32 reg;
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u32 mask_size;
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u32 eqcr_pi;
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spin_lock_init(&p->access_spinlock);
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if (!p)
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return NULL;
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@ -255,25 +278,38 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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p->addr_cena = d->cena_bar;
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p->addr_cinh = d->cinh_bar;
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if ((p->desc->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000)
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memset(p->addr_cena, 0, 64 * 1024);
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if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_5000) {
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reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
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1, /* Writes Non-cacheable */
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0, /* EQCR_CI stashing threshold */
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3, /* RPM: Valid bit mode, RCR in array mode */
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2, /* DCM: Discrete consumption ack mode */
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3, /* EPM: Valid bit mode, EQCR in array mode */
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1, /* mem stashing drop enable == TRUE */
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1, /* mem stashing priority == TRUE */
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1, /* mem stashing enable == TRUE */
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1, /* dequeue stashing priority == TRUE */
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0, /* dequeue stashing enable == FALSE */
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0); /* EQCR_CI stashing priority == FALSE */
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if ((p->desc->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000)
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reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
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1, /* Writes Non-cacheable */
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0, /* EQCR_CI stashing threshold */
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3, /* RPM: RCR in array mode */
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2, /* DCM: Discrete consumption ack */
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2, /* EPM: EQCR in ring mode */
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1, /* mem stashing drop enable enable */
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1, /* mem stashing priority enable */
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1, /* mem stashing enable */
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1, /* dequeue stashing priority enable */
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0, /* dequeue stashing enable enable */
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0); /* EQCR_CI stashing priority enable */
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} else {
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memset(p->addr_cena, 0, 64 * 1024);
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reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
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1, /* Writes Non-cacheable */
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1, /* EQCR_CI stashing threshold */
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3, /* RPM: RCR in array mode */
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2, /* DCM: Discrete consumption ack */
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0, /* EPM: EQCR in ring mode */
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1, /* mem stashing drop enable */
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1, /* mem stashing priority enable */
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1, /* mem stashing enable */
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1, /* dequeue stashing priority enable */
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0, /* dequeue stashing enable */
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0); /* EQCR_CI stashing priority enable */
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reg |= 1 << SWP_CFG_CPBS_SHIFT | /* memory-backed mode */
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1 << SWP_CFG_VPM_SHIFT | /* VDQCR read triggered mode */
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1 << SWP_CFG_CPM_SHIFT; /* CR read triggered mode */
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}
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qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
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reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
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@ -295,7 +331,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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*/
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qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
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p->eqcr.pi_ring_size = 8;
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if ((p->desc->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000) {
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p->eqcr.pi_ring_size = 32;
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qbman_swp_enqueue_ptr =
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qbman_swp_enqueue_mem_back;
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qbman_swp_enqueue_multiple_ptr =
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@ -307,6 +345,15 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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qbman_swp_release_ptr = qbman_swp_release_mem_back;
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}
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for (mask_size = p->eqcr.pi_ring_size; mask_size > 0; mask_size >>= 1)
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p->eqcr.pi_ci_mask = (p->eqcr.pi_ci_mask << 1) + 1;
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eqcr_pi = qbman_read_register(p, QBMAN_CINH_SWP_EQCR_PI);
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p->eqcr.pi = eqcr_pi & p->eqcr.pi_ci_mask;
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p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT;
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p->eqcr.ci = qbman_read_register(p, QBMAN_CINH_SWP_EQCR_CI)
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& p->eqcr.pi_ci_mask;
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p->eqcr.available = p->eqcr.pi_ring_size;
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return p;
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}
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@ -460,6 +507,7 @@ enum qb_enqueue_commands {
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#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
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#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
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#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
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#define QB_ENQUEUE_CMD_DCA_EN_SHIFT 7
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/**
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* qbman_eq_desc_clear() - Clear the contents of a descriptor to
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@ -535,6 +583,7 @@ static inline void qbman_write_eqcr_am_rt_register(struct qbman_swp *p,
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QMAN_RT_MODE);
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}
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#define QB_RT_BIT ((u32)0x100)
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/**
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* qbman_swp_enqueue_direct() - Issue an enqueue command
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* @s: the software portal used for enqueue
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@ -546,34 +595,19 @@ static inline void qbman_write_eqcr_am_rt_register(struct qbman_swp *p,
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*
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* Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
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*/
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int qbman_swp_enqueue_direct(struct qbman_swp *s, const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd)
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static
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int qbman_swp_enqueue_direct(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd)
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{
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struct qbman_eq_desc_with_fd *p;
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u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
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int flags = 0;
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int ret = qbman_swp_enqueue_multiple_direct(s, d, fd, &flags, 1);
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if (!EQAR_SUCCESS(eqar))
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return -EBUSY;
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p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
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/* This is mapped as DEVICE type memory, writes are
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* with address alignment:
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* desc.dca address alignment = 1
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* desc.seqnum address alignment = 2
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* desc.orpid address alignment = 4
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* desc.tgtid address alignment = 8
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*/
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p->desc.dca = d->dca;
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p->desc.seqnum = d->seqnum;
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p->desc.orpid = d->orpid;
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memcpy(&p->desc.tgtid, &d->tgtid, 24);
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memcpy(&p->fd, fd, sizeof(*fd));
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/* Set the verb byte, have to substitute in the valid-bit */
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dma_wmb();
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p->desc.verb = d->verb | EQAR_VB(eqar);
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return 0;
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if (ret >= 0)
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ret = 0;
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else
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ret = -EBUSY;
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return ret;
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}
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/**
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@ -587,35 +621,19 @@ int qbman_swp_enqueue_direct(struct qbman_swp *s, const struct qbman_eq_desc *d,
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*
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* Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
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*/
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static
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int qbman_swp_enqueue_mem_back(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd)
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{
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struct qbman_eq_desc_with_fd *p;
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u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
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int flags = 0;
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int ret = qbman_swp_enqueue_multiple_mem_back(s, d, fd, &flags, 1);
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if (!EQAR_SUCCESS(eqar))
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return -EBUSY;
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p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
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/* This is mapped as DEVICE type memory, writes are
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* with address alignment:
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* desc.dca address alignment = 1
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* desc.seqnum address alignment = 2
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* desc.orpid address alignment = 4
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* desc.tgtid address alignment = 8
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*/
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p->desc.dca = d->dca;
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p->desc.seqnum = d->seqnum;
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p->desc.orpid = d->orpid;
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memcpy(&p->desc.tgtid, &d->tgtid, 24);
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memcpy(&p->fd, fd, sizeof(*fd));
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p->desc.verb = d->verb | EQAR_VB(eqar);
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dma_wmb();
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qbman_write_eqcr_am_rt_register(s, EQAR_IDX(eqar));
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return 0;
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if (ret >= 0)
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ret = 0;
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else
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ret = -EBUSY;
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return ret;
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}
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/**
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@ -624,26 +642,82 @@ int qbman_swp_enqueue_mem_back(struct qbman_swp *s,
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* @s: the software portal used for enqueue
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* @d: the enqueue descriptor
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* @fd: table pointer of frame descriptor table to be enqueued
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* @flags: table pointer of flags, not used for the moment
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* @flags: table pointer of QBMAN_ENQUEUE_FLAG_DCA flags, not used if NULL
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* @num_frames: number of fd to be enqueued
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*
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* Return the number of fd enqueued, or a negative error number.
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*/
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static
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int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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uint32_t *flags,
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int num_frames)
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{
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int count = 0;
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uint32_t *p = NULL;
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const uint32_t *cl = (uint32_t *)d;
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uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;
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int i, num_enqueued = 0;
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uint64_t addr_cena;
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while (count < num_frames) {
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if (qbman_swp_enqueue_direct(s, d, fd) != 0)
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break;
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count++;
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spin_lock(&s->access_spinlock);
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half_mask = (s->eqcr.pi_ci_mask>>1);
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full_mask = s->eqcr.pi_ci_mask;
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if (!s->eqcr.available) {
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eqcr_ci = s->eqcr.ci;
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p = s->addr_cena + QBMAN_CENA_SWP_EQCR_CI;
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s->eqcr.ci = qbman_read_register(s, QBMAN_CINH_SWP_EQCR_CI);
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s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,
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eqcr_ci, s->eqcr.ci);
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if (!s->eqcr.available) {
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spin_unlock(&s->access_spinlock);
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return 0;
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}
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}
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return count;
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eqcr_pi = s->eqcr.pi;
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num_enqueued = (s->eqcr.available < num_frames) ?
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s->eqcr.available : num_frames;
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s->eqcr.available -= num_enqueued;
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/* Fill in the EQCR ring */
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for (i = 0; i < num_enqueued; i++) {
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p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
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/* Skip copying the verb */
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memcpy(&p[1], &cl[1], EQ_DESC_SIZE_WITHOUT_FD - 1);
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memcpy(&p[EQ_DESC_SIZE_FD_START/sizeof(uint32_t)],
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&fd[i], sizeof(*fd));
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eqcr_pi++;
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}
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dma_wmb();
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/* Set the verb byte, have to substitute in the valid-bit */
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eqcr_pi = s->eqcr.pi;
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for (i = 0; i < num_enqueued; i++) {
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p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
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p[0] = cl[0] | s->eqcr.pi_vb;
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if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) {
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struct qbman_eq_desc *d = (struct qbman_eq_desc *)p;
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d->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) |
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((flags[i]) & QBMAN_EQCR_DCA_IDXMASK);
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}
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eqcr_pi++;
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if (!(eqcr_pi & half_mask))
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s->eqcr.pi_vb ^= QB_VALID_BIT;
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}
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/* Flush all the cacheline without load/store in between */
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eqcr_pi = s->eqcr.pi;
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addr_cena = (size_t)s->addr_cena;
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for (i = 0; i < num_enqueued; i++)
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eqcr_pi++;
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s->eqcr.pi = eqcr_pi & full_mask;
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spin_unlock(&s->access_spinlock);
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return num_enqueued;
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}
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/**
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@ -652,26 +726,80 @@ int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s,
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* @s: the software portal used for enqueue
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* @d: the enqueue descriptor
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* @fd: table pointer of frame descriptor table to be enqueued
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* @flags: table pointer of flags, not used for the moment
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* @flags: table pointer of QBMAN_ENQUEUE_FLAG_DCA flags, not used if NULL
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* @num_frames: number of fd to be enqueued
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*
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* Return the number of fd enqueued, or a negative error number.
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*/
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static
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int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s,
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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uint32_t *flags,
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int num_frames)
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const struct qbman_eq_desc *d,
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const struct dpaa2_fd *fd,
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uint32_t *flags,
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int num_frames)
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{
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int count = 0;
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uint32_t *p = NULL;
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const uint32_t *cl = (uint32_t *)(d);
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uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;
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int i, num_enqueued = 0;
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unsigned long irq_flags;
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while (count < num_frames) {
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if (qbman_swp_enqueue_mem_back(s, d, fd) != 0)
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break;
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count++;
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spin_lock(&s->access_spinlock);
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local_irq_save(irq_flags);
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half_mask = (s->eqcr.pi_ci_mask>>1);
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full_mask = s->eqcr.pi_ci_mask;
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if (!s->eqcr.available) {
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eqcr_ci = s->eqcr.ci;
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p = s->addr_cena + QBMAN_CENA_SWP_EQCR_CI_MEMBACK;
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s->eqcr.ci = __raw_readl(p) & full_mask;
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s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,
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eqcr_ci, s->eqcr.ci);
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if (!s->eqcr.available) {
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local_irq_restore(irq_flags);
|
||||
spin_unlock(&s->access_spinlock);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return count;
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
num_enqueued = (s->eqcr.available < num_frames) ?
|
||||
s->eqcr.available : num_frames;
|
||||
s->eqcr.available -= num_enqueued;
|
||||
/* Fill in the EQCR ring */
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
/* Skip copying the verb */
|
||||
memcpy(&p[1], &cl[1], EQ_DESC_SIZE_WITHOUT_FD - 1);
|
||||
memcpy(&p[EQ_DESC_SIZE_FD_START/sizeof(uint32_t)],
|
||||
&fd[i], sizeof(*fd));
|
||||
eqcr_pi++;
|
||||
}
|
||||
|
||||
/* Set the verb byte, have to substitute in the valid-bit */
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
p[0] = cl[0] | s->eqcr.pi_vb;
|
||||
if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) {
|
||||
struct qbman_eq_desc *d = (struct qbman_eq_desc *)p;
|
||||
|
||||
d->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) |
|
||||
((flags[i]) & QBMAN_EQCR_DCA_IDXMASK);
|
||||
}
|
||||
eqcr_pi++;
|
||||
if (!(eqcr_pi & half_mask))
|
||||
s->eqcr.pi_vb ^= QB_VALID_BIT;
|
||||
}
|
||||
s->eqcr.pi = eqcr_pi & full_mask;
|
||||
|
||||
dma_wmb();
|
||||
qbman_write_register(s, QBMAN_CINH_SWP_EQCR_PI,
|
||||
(QB_RT_BIT)|(s->eqcr.pi)|s->eqcr.pi_vb);
|
||||
local_irq_restore(irq_flags);
|
||||
spin_unlock(&s->access_spinlock);
|
||||
|
||||
return num_enqueued;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -684,20 +812,66 @@ int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s,
|
|||
*
|
||||
* Return the number of fd enqueued, or a negative error number.
|
||||
*/
|
||||
static
|
||||
int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s,
|
||||
const struct qbman_eq_desc *d,
|
||||
const struct dpaa2_fd *fd,
|
||||
int num_frames)
|
||||
{
|
||||
int count = 0;
|
||||
uint32_t *p;
|
||||
const uint32_t *cl;
|
||||
uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;
|
||||
int i, num_enqueued = 0;
|
||||
uint64_t addr_cena;
|
||||
|
||||
while (count < num_frames) {
|
||||
if (qbman_swp_enqueue_direct(s, &(d[count]), fd) != 0)
|
||||
break;
|
||||
count++;
|
||||
half_mask = (s->eqcr.pi_ci_mask>>1);
|
||||
full_mask = s->eqcr.pi_ci_mask;
|
||||
if (!s->eqcr.available) {
|
||||
eqcr_ci = s->eqcr.ci;
|
||||
p = s->addr_cena + QBMAN_CENA_SWP_EQCR_CI;
|
||||
s->eqcr.ci = qbman_read_register(s, QBMAN_CINH_SWP_EQCR_CI);
|
||||
s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,
|
||||
eqcr_ci, s->eqcr.ci);
|
||||
if (!s->eqcr.available)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return count;
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
num_enqueued = (s->eqcr.available < num_frames) ?
|
||||
s->eqcr.available : num_frames;
|
||||
s->eqcr.available -= num_enqueued;
|
||||
/* Fill in the EQCR ring */
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
cl = (uint32_t *)(&d[i]);
|
||||
/* Skip copying the verb */
|
||||
memcpy(&p[1], &cl[1], EQ_DESC_SIZE_WITHOUT_FD - 1);
|
||||
memcpy(&p[EQ_DESC_SIZE_FD_START/sizeof(uint32_t)],
|
||||
&fd[i], sizeof(*fd));
|
||||
eqcr_pi++;
|
||||
}
|
||||
|
||||
dma_wmb();
|
||||
|
||||
/* Set the verb byte, have to substitute in the valid-bit */
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
cl = (uint32_t *)(&d[i]);
|
||||
p[0] = cl[0] | s->eqcr.pi_vb;
|
||||
eqcr_pi++;
|
||||
if (!(eqcr_pi & half_mask))
|
||||
s->eqcr.pi_vb ^= QB_VALID_BIT;
|
||||
}
|
||||
|
||||
/* Flush all the cacheline without load/store in between */
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
addr_cena = (uint64_t)s->addr_cena;
|
||||
for (i = 0; i < num_enqueued; i++)
|
||||
eqcr_pi++;
|
||||
s->eqcr.pi = eqcr_pi & full_mask;
|
||||
|
||||
return num_enqueued;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -710,20 +884,62 @@ int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s,
|
|||
*
|
||||
* Return the number of fd enqueued, or a negative error number.
|
||||
*/
|
||||
static
|
||||
int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s,
|
||||
const struct qbman_eq_desc *d,
|
||||
const struct dpaa2_fd *fd,
|
||||
int num_frames)
|
||||
{
|
||||
int count = 0;
|
||||
uint32_t *p;
|
||||
const uint32_t *cl;
|
||||
uint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;
|
||||
int i, num_enqueued = 0;
|
||||
|
||||
while (count < num_frames) {
|
||||
if (qbman_swp_enqueue_mem_back(s, &(d[count]), fd) != 0)
|
||||
break;
|
||||
count++;
|
||||
half_mask = (s->eqcr.pi_ci_mask>>1);
|
||||
full_mask = s->eqcr.pi_ci_mask;
|
||||
if (!s->eqcr.available) {
|
||||
eqcr_ci = s->eqcr.ci;
|
||||
p = s->addr_cena + QBMAN_CENA_SWP_EQCR_CI_MEMBACK;
|
||||
s->eqcr.ci = __raw_readl(p) & full_mask;
|
||||
s->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,
|
||||
eqcr_ci, s->eqcr.ci);
|
||||
if (!s->eqcr.available)
|
||||
return 0;
|
||||
}
|
||||
|
||||
return count;
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
num_enqueued = (s->eqcr.available < num_frames) ?
|
||||
s->eqcr.available : num_frames;
|
||||
s->eqcr.available -= num_enqueued;
|
||||
/* Fill in the EQCR ring */
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
cl = (uint32_t *)(&d[i]);
|
||||
/* Skip copying the verb */
|
||||
memcpy(&p[1], &cl[1], EQ_DESC_SIZE_WITHOUT_FD - 1);
|
||||
memcpy(&p[EQ_DESC_SIZE_FD_START/sizeof(uint32_t)],
|
||||
&fd[i], sizeof(*fd));
|
||||
eqcr_pi++;
|
||||
}
|
||||
|
||||
/* Set the verb byte, have to substitute in the valid-bit */
|
||||
eqcr_pi = s->eqcr.pi;
|
||||
for (i = 0; i < num_enqueued; i++) {
|
||||
p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));
|
||||
cl = (uint32_t *)(&d[i]);
|
||||
p[0] = cl[0] | s->eqcr.pi_vb;
|
||||
eqcr_pi++;
|
||||
if (!(eqcr_pi & half_mask))
|
||||
s->eqcr.pi_vb ^= QB_VALID_BIT;
|
||||
}
|
||||
|
||||
s->eqcr.pi = eqcr_pi & full_mask;
|
||||
|
||||
dma_wmb();
|
||||
qbman_write_register(s, QBMAN_CINH_SWP_EQCR_PI,
|
||||
(QB_RT_BIT)|(s->eqcr.pi)|s->eqcr.pi_vb);
|
||||
|
||||
return num_enqueued;
|
||||
}
|
||||
|
||||
/* Static (push) dequeue */
|
||||
|
|
@ -889,6 +1105,7 @@ void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
|
|||
* Return 0 for success, and -EBUSY if the software portal is not ready
|
||||
* to do pull dequeue.
|
||||
*/
|
||||
static
|
||||
int qbman_swp_pull_direct(struct qbman_swp *s, struct qbman_pull_desc *d)
|
||||
{
|
||||
struct qbman_pull_desc *p;
|
||||
|
|
@ -924,6 +1141,7 @@ int qbman_swp_pull_direct(struct qbman_swp *s, struct qbman_pull_desc *d)
|
|||
* Return 0 for success, and -EBUSY if the software portal is not ready
|
||||
* to do pull dequeue.
|
||||
*/
|
||||
static
|
||||
int qbman_swp_pull_mem_back(struct qbman_swp *s, struct qbman_pull_desc *d)
|
||||
{
|
||||
struct qbman_pull_desc *p;
|
||||
|
|
@ -942,6 +1160,8 @@ int qbman_swp_pull_mem_back(struct qbman_swp *s, struct qbman_pull_desc *d)
|
|||
p->dq_src = d->dq_src;
|
||||
p->rsp_addr = d->rsp_addr;
|
||||
p->rsp_addr_virt = d->rsp_addr_virt;
|
||||
|
||||
/* Set the verb byte, have to substitute in the valid-bit */
|
||||
p->verb = d->verb | s->vdq.valid_bit;
|
||||
s->vdq.valid_bit ^= QB_VALID_BIT;
|
||||
dma_wmb();
|
||||
|
|
|
|||
|
|
@ -143,6 +143,19 @@ struct qbman_swp {
|
|||
u8 dqrr_size;
|
||||
int reset_bug; /* indicates dqrr reset workaround is needed */
|
||||
} dqrr;
|
||||
|
||||
struct {
|
||||
u32 pi;
|
||||
u32 pi_vb;
|
||||
u32 pi_ring_size;
|
||||
u32 pi_ci_mask;
|
||||
u32 ci;
|
||||
int available;
|
||||
u32 pend;
|
||||
u32 no_pfdr;
|
||||
} eqcr;
|
||||
|
||||
spinlock_t access_spinlock;
|
||||
};
|
||||
|
||||
/* Function pointers */
|
||||
|
|
|
|||
Loading…
Reference in New Issue