From ff9a6262b9b87204146427a3abefc73ab990c21f Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 3 Jun 2015 14:18:21 +0100 Subject: [PATCH 1/4] arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno This patch adds support for the MHU mailbox peripheral used on Juno by application processors to communicate with remote SCP handling most of the CPU/system power management. It also adds the SRAM reserving the shared memory and SCPI message protocol using that shared memory. Signed-off-by: Sudeep Holla Acked-by: Liviu Dudau Cc: Jon Medhurst (Tixy) --- arch/arm64/boot/dts/arm/juno-base.dtsi | 54 ++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index e3ee96036eca..c624208edef6 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -17,6 +17,18 @@ frame@2a830000 { }; }; + mailbox: mhu@2b1f0000 { + compatible = "arm,mhu", "arm,primecell"; + reg = <0x0 0x2b1f0000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "mhu_lpri_rx", + "mhu_hpri_rx"; + #mbox-cells = <1>; + clocks = <&soc_refclk100mhz>; + clock-names = "apb_pclk"; + }; + gic: interrupt-controller@2c010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; reg = <0x0 0x2c010000 0 0x1000>, @@ -44,6 +56,48 @@ timer { ; }; + sram: sram@2e000000 { + compatible = "arm,juno-sram-ns", "mmio-sram"; + reg = <0x0 0x2e000000 0x0 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2e000000 0x8000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "arm,juno-scp-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "arm,juno-scp-shmem"; + reg = <0x200 0x200>; + }; + }; + + scpi { + compatible = "arm,scpi"; + mboxes = <&mailbox 1>; + shmem = <&cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "atlclk", "aplclk","gpuclk"; + }; + scpi_clk: scpi_clocks@3 { + compatible = "arm,scpi-variable-clocks"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + }; + }; + /include/ "juno-clocks.dtsi" dma@7ff00000 { From 050c69e8769b00645d6723390de6092c9dfcf746 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 3 Jun 2015 14:31:49 +0100 Subject: [PATCH 2/4] arm64: dts: add CPU topology on Juno This patch adds CPU topology on Juno. It will be useful for ther other IP blocks depending on this topology. Signed-off-by: Sudeep Holla Acked-by: Liviu Dudau Cc: Jon Medhurst (Tixy) --- arch/arm64/boot/dts/arm/juno-r1.dts | 26 ++++++++++++++++++++++++++ arch/arm64/boot/dts/arm/juno.dts | 26 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index c62751153a4f..69130840c6cd 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -34,6 +34,32 @@ cpus { #address-cells = <2>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index d7cbdd482a61..ce1128a54c8d 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -34,6 +34,32 @@ cpus { #address-cells = <2>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&A57_0>; + }; + core1 { + cpu = <&A57_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + }; + A57_0: cpu@0 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x0 0x0>; From a738459888b361c10b585629b84b0d0e6e7cbb27 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 3 Jun 2015 14:40:56 +0100 Subject: [PATCH 3/4] arm64: dts: add clock support for all the cpus This patch adds the CPU clocks so that the CPU DVFS can be enabled. Signed-off-by: Sudeep Holla Acked-by: Liviu Dudau Cc: Jon Medhurst (Tixy) --- arch/arm64/boot/dts/arm/juno-r1.dts | 6 ++++++ arch/arm64/boot/dts/arm/juno.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 69130840c6cd..5eef4aa0c532 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -66,6 +66,7 @@ A57_0: cpu@0 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; }; A57_1: cpu@1 { @@ -74,6 +75,7 @@ A57_1: cpu@1 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; }; A53_0: cpu@100 { @@ -82,6 +84,7 @@ A53_0: cpu@100 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_1: cpu@101 { @@ -90,6 +93,7 @@ A53_1: cpu@101 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_2: cpu@102 { @@ -98,6 +102,7 @@ A53_2: cpu@102 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_3: cpu@103 { @@ -106,6 +111,7 @@ A53_3: cpu@103 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A57_L2: l2-cache0 { diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index ce1128a54c8d..c02f880584e8 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -66,6 +66,7 @@ A57_0: cpu@0 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; }; A57_1: cpu@1 { @@ -74,6 +75,7 @@ A57_1: cpu@1 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A57_L2>; + clocks = <&scpi_dvfs 0>; }; A53_0: cpu@100 { @@ -82,6 +84,7 @@ A53_0: cpu@100 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_1: cpu@101 { @@ -90,6 +93,7 @@ A53_1: cpu@101 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_2: cpu@102 { @@ -98,6 +102,7 @@ A53_2: cpu@102 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A53_3: cpu@103 { @@ -106,6 +111,7 @@ A53_3: cpu@103 { device_type = "cpu"; enable-method = "psci"; next-level-cache = <&A53_L2>; + clocks = <&scpi_dvfs 1>; }; A57_L2: l2-cache0 { From dfacaf0e7cbe9f845459f3332f94cdbc368932af Mon Sep 17 00:00:00 2001 From: Punit Agrawal Date: Tue, 15 Sep 2015 17:51:01 +0100 Subject: [PATCH 4/4] arm64: dts: Add sensor node to Juno dt The SCP firmware on Juno provides access to SoC sensors via the SCPI. Add the sensor nodes to the device tree to enable this support. Signed-off-by: Punit Agrawal Cc: Rob Herring Cc: Mark Rutland Acked-by: Sudeep Holla Acked-by: Liviu Dudau --- arch/arm64/boot/dts/arm/juno-base.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index c624208edef6..dd5158eb5872 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -96,6 +96,11 @@ scpi_clk: scpi_clocks@3 { clock-output-names = "pxlclk0", "pxlclk1"; }; }; + + scpi_sensors0: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; }; /include/ "juno-clocks.dtsi"