mirror of https://gitee.com/openkylin/linux.git
pxafb: preliminary smart panel interface support
Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Eric Miao
Linus Torvalds
parent
90eabbf0ec
commit
3c42a44910
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@ -1774,6 +1774,11 @@ config FB_PXA
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If unsure, say N.
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config FB_PXA_SMARTPANEL
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bool "PXA Smartpanel LCD support"
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default y
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depends on FB_PXA
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config FB_PXA_PARAMETERS
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bool "PXA LCD command line parameters"
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default n
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@ -40,6 +40,8 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/completion.h>
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#include <linux/kthread.h>
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#include <linux/freezer.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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@ -455,7 +457,7 @@ static int pxafb_mmap(struct fb_info *info,
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unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
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if (off < info->fix.smem_len) {
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vma->vm_pgoff += 1;
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vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
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return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
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fbi->map_dma, fbi->map_size);
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}
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@ -594,6 +596,183 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
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return 0;
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}
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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static int setup_smart_dma(struct pxafb_info *fbi)
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{
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struct pxafb_dma_descriptor *dma_desc;
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unsigned long dma_desc_off, cmd_buff_off;
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dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
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dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
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cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
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dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
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dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
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dma_desc->fidr = 0;
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dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
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fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
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return 0;
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}
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int pxafb_smart_flush(struct fb_info *info)
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{
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struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
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uint32_t prsr;
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int ret = 0;
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/* disable controller until all registers are set up */
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lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
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/* 1. make it an even number of commands to align on 32-bit boundary
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* 2. add the interrupt command to the end of the chain so we can
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* keep track of the end of the transfer
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*/
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while (fbi->n_smart_cmds & 1)
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fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
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fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
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fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
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setup_smart_dma(fbi);
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/* continue to execute next command */
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prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
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lcd_writel(fbi, PRSR, prsr);
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/* stop the processor in case it executed "wait for sync" cmd */
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lcd_writel(fbi, CMDCR, 0x0001);
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/* don't send interrupts for fifo underruns on channel 6 */
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lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
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lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
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lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
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lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
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lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
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lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
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/* begin sending */
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lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
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if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
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pr_warning("%s: timeout waiting for command done\n",
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__func__);
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ret = -ETIMEDOUT;
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}
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/* quick disable */
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prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
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lcd_writel(fbi, PRSR, prsr);
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lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
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lcd_writel(fbi, FDADR6, 0);
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fbi->n_smart_cmds = 0;
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return ret;
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}
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int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
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{
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int i;
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struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
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/* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
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for (i = 0; i < n_cmds; i++) {
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if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
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pxafb_smart_flush(info);
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fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
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}
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return 0;
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}
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static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
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{
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unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
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return (t == 0) ? 1 : t;
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}
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static void setup_smart_timing(struct pxafb_info *fbi,
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struct fb_var_screeninfo *var)
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{
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struct pxafb_mach_info *inf = fbi->dev->platform_data;
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struct pxafb_mode_info *mode = &inf->modes[0];
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unsigned long lclk = clk_get_rate(fbi->clk);
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unsigned t1, t2, t3, t4;
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t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
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t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
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t3 = mode->op_hold_time;
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t4 = mode->cmd_inh_time;
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fbi->reg_lccr1 =
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LCCR1_DisWdth(var->xres) |
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LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
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LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
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LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
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fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
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fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
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/* FIXME: make this configurable */
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fbi->reg_cmdcr = 1;
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}
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static int pxafb_smart_thread(void *arg)
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{
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struct pxafb_info *fbi = (struct pxafb_info *) arg;
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struct pxafb_mach_info *inf = fbi->dev->platform_data;
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if (!fbi || !inf->smart_update) {
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pr_err("%s: not properly initialized, thread terminated\n",
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__func__);
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return -EINVAL;
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}
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pr_debug("%s(): task starting\n", __func__);
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set_freezable();
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while (!kthread_should_stop()) {
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if (try_to_freeze())
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continue;
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if (fbi->state == C_ENABLE) {
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inf->smart_update(&fbi->fb);
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complete(&fbi->refresh_done);
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}
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set_current_state(TASK_INTERRUPTIBLE);
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schedule_timeout(30 * HZ / 1000);
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}
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pr_debug("%s(): task ending\n", __func__);
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return 0;
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}
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static int pxafb_smart_init(struct pxafb_info *fbi)
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{
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fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
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"lcd_refresh");
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if (IS_ERR(fbi->smart_thread)) {
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printk(KERN_ERR "%s: unable to create kernel thread\n",
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__func__);
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return PTR_ERR(fbi->smart_thread);
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}
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return 0;
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}
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#else
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int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
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{
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return 0;
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}
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int pxafb_smart_flush(struct fb_info *info)
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{
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return 0;
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}
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#endif /* CONFIG_FB_SMART_PANEL */
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static void setup_parallel_timing(struct pxafb_info *fbi,
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struct fb_var_screeninfo *var)
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{
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@ -643,6 +822,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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size_t nbytes;
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#if DEBUG_VAR
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if (!(fbi->lccr0 & LCCR0_LCDT)) {
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if (var->xres < 16 || var->xres > 1024)
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printk(KERN_ERR "%s: invalid xres %d\n",
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fbi->fb.fix.id, var->xres);
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@ -658,6 +838,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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fbi->fb.fix.id, var->bits_per_pixel);
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break;
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}
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if (var->hsync_len < 1 || var->hsync_len > 64)
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printk(KERN_ERR "%s: invalid hsync_len %d\n",
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fbi->fb.fix.id, var->hsync_len);
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@ -679,10 +860,16 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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if (var->lower_margin < 0 || var->lower_margin > 255)
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printk(KERN_ERR "%s: invalid lower_margin %d\n",
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fbi->fb.fix.id, var->lower_margin);
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}
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#endif
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/* Update shadow copy atomically */
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local_irq_save(flags);
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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if (fbi->lccr0 & LCCR0_LCDT)
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setup_smart_timing(fbi, var);
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else
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#endif
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setup_parallel_timing(fbi, var);
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fbi->reg_lccr0 = fbi->lccr0 |
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@ -698,7 +885,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
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setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
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}
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if (var->bits_per_pixel >= 16)
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if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
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setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
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else
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setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
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@ -801,6 +988,9 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
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/* enable LCD controller clock */
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clk_enable(fbi->clk);
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if (fbi->lccr0 & LCCR0_LCDT)
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return;
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/* Sequence from 11.7.10 */
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lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
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lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
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@ -816,6 +1006,14 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
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{
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uint32_t lccr0;
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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if (fbi->lccr0 & LCCR0_LCDT) {
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wait_for_completion_timeout(&fbi->refresh_done,
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200 * HZ / 1000);
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return;
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}
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#endif
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/* Clear LCD Status Register */
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lcd_writel(fbi, LCSR, 0xffffffff);
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@ -843,6 +1041,11 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
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complete(&fbi->disable_done);
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}
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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if (lcsr & LCSR_CMD_INT)
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complete(&fbi->command_done);
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#endif
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lcd_writel(fbi, LCSR, lcsr);
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return IRQ_HANDLED;
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}
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@ -1050,15 +1253,17 @@ static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
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* We reserve one page for the palette, plus the size
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* of the framebuffer.
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*/
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fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
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fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
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fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
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fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
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&fbi->map_dma, GFP_KERNEL);
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if (fbi->map_cpu) {
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/* prevent initial garbage on screen */
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memset(fbi->map_cpu, 0, fbi->map_size);
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fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
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fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
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fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
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fbi->screen_dma = fbi->map_dma + fbi->video_offset;
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/*
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* FIXME: this is actually the wrong thing to place in
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* smem_start. But fbdev suffers from the problem that
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@ -1070,7 +1275,12 @@ static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
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fbi->dma_buff = (void *) fbi->map_cpu;
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fbi->dma_buff_phys = fbi->map_dma;
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fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
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fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
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fbi->n_smart_cmds = 0;
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#endif
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}
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return fbi->map_cpu ? 0 : -ENOMEM;
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@ -1191,6 +1401,10 @@ static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
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INIT_WORK(&fbi->task, pxafb_task);
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init_MUTEX(&fbi->ctrlr_sem);
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init_completion(&fbi->disable_done);
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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init_completion(&fbi->command_done);
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init_completion(&fbi->refresh_done);
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#endif
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return fbi;
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}
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@ -1510,6 +1724,13 @@ static int __init pxafb_probe(struct platform_device *dev)
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goto failed_free_mem;
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}
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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ret = pxafb_smart_init(fbi);
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if (ret) {
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dev_err(&dev->dev, "failed to initialize smartpanel\n");
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goto failed_free_irq;
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}
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#endif
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/*
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* This makes sure that our colour bitfield
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* descriptors are correctly initialised.
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@ -52,9 +52,11 @@ enum {
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/* maximum palette size - 256 entries, each 4 bytes long */
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#define PALETTE_SIZE (256 * 4)
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#define CMD_BUFF_SIZE (1024 * 50)
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struct pxafb_dma_buff {
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unsigned char palette[PAL_MAX * PALETTE_SIZE];
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uint16_t cmd_buff[CMD_BUFF_SIZE];
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struct pxafb_dma_descriptor pal_desc[PAL_MAX];
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struct pxafb_dma_descriptor dma_desc[DMA_MAX];
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};
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@ -84,6 +86,7 @@ struct pxafb_info {
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dma_addr_t screen_dma; /* physical address of frame buffer */
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u16 * palette_cpu; /* virtual address of palette memory */
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u_int palette_size;
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ssize_t video_offset;
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u_int lccr0;
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u_int lccr3;
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@ -97,6 +100,7 @@ struct pxafb_info {
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u_int reg_lccr2;
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u_int reg_lccr3;
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u_int reg_lccr4;
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u_int reg_cmdcr;
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unsigned long hsync_time;
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@ -108,6 +112,14 @@ struct pxafb_info {
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struct completion disable_done;
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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uint16_t *smart_cmds;
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size_t n_smart_cmds;
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struct completion command_done;
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struct completion refresh_done;
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struct task_struct *smart_thread;
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#endif
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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struct notifier_block freq_policy;
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@ -48,6 +48,7 @@
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#define LCD_COLOR_DSTN_16BPP ((16 << 4) | LCD_TYPE_COLOR_DSTN)
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#define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
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#define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
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#define LCD_SMART_PANEL_8BPP ((8 << 4) | LCD_TYPE_SMART_PANEL)
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#define LCD_SMART_PANEL_16BPP ((16 << 4) | LCD_TYPE_SMART_PANEL)
|
||||
#define LCD_SMART_PANEL_18BPP ((18 << 4) | LCD_TYPE_SMART_PANEL)
|
||||
|
||||
|
|
@ -69,6 +70,10 @@ struct pxafb_mode_info {
|
|||
u_short yres;
|
||||
|
||||
u_char bpp;
|
||||
u_int cmap_greyscale:1,
|
||||
unused:31;
|
||||
|
||||
/* Parallel Mode Timing */
|
||||
u_char hsync_len;
|
||||
u_char left_margin;
|
||||
u_char right_margin;
|
||||
|
|
@ -78,8 +83,20 @@ struct pxafb_mode_info {
|
|||
u_char lower_margin;
|
||||
u_char sync;
|
||||
|
||||
u_int cmap_greyscale:1,
|
||||
unused:31;
|
||||
/* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
|
||||
* Note:
|
||||
* 1. all parameters in nanosecond (ns)
|
||||
* 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
|
||||
* in pxa27x and pxa3xx, initialize them to the same value or
|
||||
* the larger one will be used
|
||||
* 3. same to {rd,wr}_pulse_width
|
||||
*/
|
||||
unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
|
||||
unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
|
||||
unsigned wr_pulse_width; /* L_PCLK_WR pulse width */
|
||||
unsigned rd_pulse_width; /* L_FCLK_RD pulse width */
|
||||
unsigned cmd_inh_time; /* Command Inhibit time between two writes */
|
||||
unsigned op_hold_time; /* Output Hold time from L_FCLK_RD negation */
|
||||
};
|
||||
|
||||
struct pxafb_mach_info {
|
||||
|
|
@ -123,8 +140,11 @@ struct pxafb_mach_info {
|
|||
u_int lccr4;
|
||||
void (*pxafb_backlight_power)(int);
|
||||
void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
|
||||
|
||||
void (*smart_update)(struct fb_info *);
|
||||
};
|
||||
void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
|
||||
void set_pxa_fb_parent(struct device *parent_dev);
|
||||
unsigned long pxafb_get_hsync_time(struct device *dev);
|
||||
|
||||
extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
|
||||
extern int pxafb_smart_flush(struct fb_info *info);
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@
|
|||
#define LCCR1 (0x004) /* LCD Controller Control Register 1 */
|
||||
#define LCCR2 (0x008) /* LCD Controller Control Register 2 */
|
||||
#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
|
||||
#define LCCR4 (0x010) /* LCD Controller Control Register 3 */
|
||||
#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
|
||||
#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
|
||||
#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
|
||||
#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
|
||||
#define LCSR (0x038) /* LCD Controller Status Register */
|
||||
|
|
@ -15,6 +16,9 @@
|
|||
#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
|
||||
#define TMEDCR (0x044) /* TMED Control Register */
|
||||
|
||||
#define CMDCR (0x100) /* Command Control Register */
|
||||
#define PRSR (0x104) /* Panel Read Status Register */
|
||||
|
||||
#define LCCR3_1BPP (0 << 24)
|
||||
#define LCCR3_2BPP (1 << 24)
|
||||
#define LCCR3_4BPP (2 << 24)
|
||||
|
|
@ -39,6 +43,9 @@
|
|||
#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */
|
||||
#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */
|
||||
#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */
|
||||
#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
|
||||
#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */
|
||||
#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */
|
||||
|
||||
#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
|
||||
#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
|
||||
|
|
@ -122,6 +129,11 @@
|
|||
#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
|
||||
#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
|
||||
|
||||
#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */
|
||||
#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */
|
||||
#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */
|
||||
#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */
|
||||
|
||||
#define LCSR_LDD (1 << 0) /* LCD Disable Done */
|
||||
#define LCSR_SOF (1 << 1) /* Start of frame */
|
||||
#define LCSR_BER (1 << 2) /* Bus error */
|
||||
|
|
@ -133,7 +145,27 @@
|
|||
#define LCSR_EOF (1 << 8) /* end of frame */
|
||||
#define LCSR_BS (1 << 9) /* branch status */
|
||||
#define LCSR_SINT (1 << 10) /* subsequent interrupt */
|
||||
#define LCSR_RD_ST (1 << 11) /* read status */
|
||||
#define LCSR_CMD_INT (1 << 12) /* command interrupt */
|
||||
|
||||
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
|
||||
|
||||
/* smartpanel related */
|
||||
#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
|
||||
#define PRSR_A0 (1 << 8) /* Read Data Source */
|
||||
#define PRSR_ST_OK (1 << 9) /* Status OK */
|
||||
#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */
|
||||
|
||||
#define SMART_CMD_A0 (0x1 << 8)
|
||||
#define SMART_CMD_READ_STATUS_REG (0x0 << 9)
|
||||
#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
|
||||
#define SMART_CMD_WRITE_COMMAND (0x1 << 9)
|
||||
#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
|
||||
#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
|
||||
#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
|
||||
#define SMART_CMD_NOOP (0x4 << 9)
|
||||
#define SMART_CMD_INTERRUPT (0x5 << 9)
|
||||
|
||||
#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
|
||||
#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
|
||||
#endif /* __ASM_ARCH_REGS_LCD_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue